User guide
Figure 7–2 DECchip 21071-DA Block Diagram
ML013460
4-Entry
DMA Write
Address
FIFO
DMA Read Address
DMA Write
Address
PCI ad<31:0>
Read
Bypass
MUX
3 LW DMA
Read I/O
Write Buffer
epiData<31:0>
8-Entry
TLB
PCI Window
Hit Detection
Parity Check
Generation
PCI cbe<3:0>
PCI par
epiErr<31:0>
CSRs and
Error Logging
Address
MUX and
Merge Logic
DMA Write
I/O Read Data
DMA Read
I/O Write Data
I/O
Address
adr<33:5>
The PCI host bridge serves as the interface between the PCI local bus and the
21064A microprocessor’s Bcache and main memory. It acts as a master during the
CPU-initiated transactions that use the PCI bus and is a target of transactions
initiated by other devices.
The PCI host bridge controls the buffers for various transactions. The address
and control mechanism is in the PCI host bridge; the data is stored in the
21071-BA chips.
7.1 Interface to the System Bus
7.1.1 Decoding Physical Addresses
The PCI host bridge provides address decode logic to translate from the CPU’s
34-bit physical address space to the 32-bit PCI address space. Chapter 5 shows
the address mapping and translation scheme that the address decode logic uses
to generate a PCI address. All systems using the 21071-DA are required to follow
this address mapping scheme.
7–2 PCI Host Bridge