User guide

6.7.1 Memory Read Buffer
The memory read buffer stores data from memory before the data is sent to the
CPU or returned to DMA in the DMA read buffer. Each chip stores 4 longwords
of data and the corresponding ECC bits in the memory read buffer.
6.7.2 I/O Read Buffer and Merge Buffer
On CPU-initiated memory transactions, the buffer acts as the merge buffer.
On CPU-initiated I/O read transactions addressed to or through the PCI host
bridge (the 21071-DA chip), the buffer acts as the I/O read buffer. The memory
and cache controller (21071-CA) and the PCI host bridge (21071-DA) control the
loading of data into the buffer.
Each chip stores four longwords of data and the corresponding ECC bits. The
ECC bits are only meaningful for merge data; the ECC bits are unpredictable for
I/O read data.
6.7.3 I/O Write and DMA Read Buffer
This buffer stores up to four entries of data for each chip: two entries for I/O
write data and two entries are for read data. Each entry has four longwords but
only two longwords are used; the extra storage is not accessible.
The memory and cache controller (21071-CA) handles the loading of the buffer
using the address provided on iolinesel<1:0> by the PCI host bridge (21071-DA).
Each entry can be loaded separately, allowing maximum flexibility in allocating
the entries.
The PCI host bridge controls unloading of the buffer. Data from this buffer is
sent out on the epiData bus.
6.7.4 DMA Write Buffer
In addition to storing DMA write data, the DMA write buffer stores PCI byte
masks. The buffer has four entries for each chip. Each entry has four longwords
and their byte mask but only two longwords are used; the extra storage is not
accessible. The byte masks are used to merge the valid bytes of data from the
buffer with the background data from the cache line, which may be obtained from
Bcache or memory.
On DMA write transactions, the PCI host bridge loads the buffer and the memory
and cache controller unloads it to the system bus.
Cache and Memory Subsystem 6–31