User guide

Table 6–10 (Cont.) Refresh Timing Register
Field Name Type Description
<0> DISREF RW, 0 Disable refresh. Refresh operations are not
performed when DISREF is set. The other
timings in this register must not change
while this bit is set. FORCE_REF overrides
DISREF.
6.7 Data Path
The data path consists of the buffers and their communications buses. This
section gives a functional overview of the 21071-BA chips that make up the data
bus configuration. Figure 6–21 shows a block diagram of the 21071-BA chip.
Figure 6–21 Block Diagram of the DECchip 21071-BA
ML013459
PAD
Latch
sysData
<127:0>
DMA
Write
Buffer
Memory
Write
Buffer
memData
<127:0>
Merge
I/O
Read
Buffer
Memory
Read
Buffer
ECC
Generator
DMA
Read
Buffer
I/O
Write
Buffer
epiData <31:0>
ECC
Check
6–30 Cache and Memory Subsystem