User guide

The refresh timing register is shown in Figure 6–20 and is defined in Table 6–10.
Figure 6–20 Refresh Timing Register: 0x180000220
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04194.AI
FORCE_REF
MBZ
REF_INTERVAL
REF_RASWIDTH
REF_CAS2RAS
DISREF
Table 6–10 Refresh Timing Register
Field Name Type Description
<15> FORCE_REF RW, 1 Force refresh. Reads as 0. Writing a 1 to this
bit causes a single memory refresh. Resets
the internal refresh interval counter.
<14:13> Reserved MBZ
<12:7> REF_INTERVAL RW,
000001
Indicates the extent of the refresh interval.
Multiplied by 64 to get the number of
memclk cycles between refresh requests.
A programmed value of zero is illegal.
<6:4> REF_RASWIDTH RW, 1 Refresh RAS width. Refresh RAS assertion
width from b<3:0>_ras0_l assertion to
b<3:0>_ras0_l deassertion. b<3:0>_cas0_l
is deasserted with b<3:0>_ras0_l for refresh.
Corresponds to DRAM parameter t
RAS
.
.
<3:1> REF_CAS2RAS RW, 1 Refresh CAS assertion to RAS assertion
cycles. Corresponds to DRAM parameter
t
CSR
.
.
(continued on next page)
Cache and Memory Subsystem 6–29