User guide

Figure 6–19 Global Timing Register: 0x180000200
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04193.AI
MBZ
GTR_MAX_RAS_WIDTH
GTR_RP
Table 6–9 Global Timing Register
Field Name Type Description
<15:6> Reserved MBZ —
<5:3> GTR_MAX_RAS_WIDTH — Maximum RAS assertion width as a
multiple of 128 memory clock cycles.
When this count is reached, the
signal b<3:0>_ras0_l is deasserted at
the end of the ongoing transaction.
This value must be programmed to
allow the timer to overflow during a
transaction. Corresponds to DRAM
parameter t
RAS
. When programmed
to 0, page mode between transactions
is disabled.
<2:0> GTR_RP — Minimum number of RAS precharge
cycles. Cycles extend from b<3:0>_
cas0_l deassertion to next assertion
of the same b<3:0>_cas0_l pin.
Corresponds to DRAM parameter t
RP
.
.
6.6.8.7 Refresh Timing Register
The refresh timing register contains information used to refresh all bank sets
simultaneously using CAS-before-RAS refresh. Therefore, these parameters must
be programmed to the most conservative values for all bank sets.
All the timing parameters are in multiples of memclk cycles. The parameters
have a minimum value that is added to the programmed value. In the program,
subtract this minimum value from the desired value before writing the value to
the register.
6–28 Cache and Memory Subsystem