User guide

Table 6–8 Timing Register B
Field Name Type Description
<15:14> Reserved MBZ —
<13:11> S0_WHOLD0COL RW, 1 Write hold time from column address.
Used only for the first data when starting
in page mode. Write data is valid with
the column address and is held valid for
S8_WHOLD0COL + 2 cycles after the column
address.
.
<10:8> S0_WHOLD0ROW RW, 1 Write hold time from row address. Hold
time of first write data from first row
address. Used when not starting in page
mode. The first write data is valid with
the row address and is held valid for
S8_WHOLD0ROW + 2 cycles after the row
address. A programmed value of zero is
illegal.
.
<7:6> S0_TCP RW, 1 CAS precharge (t
CP
). Delay from
b0_cas<1:0>_l deassertion to the next
assertion of b0_cas<1:0>_l in page mode.
.
<5:3> S0_WTCAS RW, 1 Write CAS width (t
CAS
). Used on write
transactions to generate the b0_cas<1:0>_l
deassertion from the assertion of
b0_cas<1:0>_l.
The sum of S8_WTCAS and S0_TCP must not
be greater than 5.
.
<2:0> S0_RTCAS RW, 1 Read CAS width (t
CAS
). Used on read transac-
tions to generate the b0_cas<1:0>_l deasser-
tion from the assertion of b0_cas<1:0>_l.
The sum of S8_RTCAS and S0_TCP must not
be greater than 5.
.
6.6.8.6 Global Timing Register
The global timing register contains parameters that are common to all bank sets.
Each parameter counts memory clock cycles. All pins on the memory interface
refer to memclk rising. The global timing register is shown in Figure 6–19 and is
defined in Table 6–9.
Cache and Memory Subsystem 6–27