User guide

Table 6–7 (Cont.) Timing Register A
Field Name Type Description
<6:4> S0_COLSETUP RW, 0 Column address setup (t
ASC
) to first CAS
assertion and write enable setup (t
CWL
)to
CAS assertion. Used to determine first
b0_cas<1:0>_l assertion after column
address and b<1:0>_cas<1:0>_l assertion
after b0_l<3:0>_we_l. The maximum of the
two setup values must be programmed. A
programmed value of 7 is illegal.
.
<3:2> S0_ROWHOLD — Row address hold. Used to switch memadr
from row to column after b<1:0>_ras_l
assertion.
.
<1:0> S0_ROWSETUP RW, 1 Row address setup. Used to generate
b<1:0>_ras0_l assertion from row address.
.
Timing register B is shown in Figure 6–18 and is defined in Table 6–8.
Figure 6–18 Bank Set 0 Timing Register B: 0x180000E00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ML013279
MBZ
S0_WHOLD0COL
S0_WHOLD0ROW
S0_TCP
S0_WTCAS
S0_RTCAS
6–26 Cache and Memory Subsystem