User guide

The description of the parameters also indicates the corresponding DRAM
parameter. Bank 0’s timing register A is shown in Figure 6–17 and is defined
in Table 6–7.
Figure 6–17 Bank Set 0 Timing Register A: 0x180000C00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ML013278
MBZ
S0_RDLYCOL
S0_RDLYROW
S0_COLHOLD
S0_COLSETUP
S0_ROWHOLD
S0_ROWSETUP
Table 6–7 Timing Register A
Field Name Type Description
<15> Reserved MBZ —
<14:12> S0_RDLYCOL RW, 1 Read delay from column address. Used only
when starting in page mode. Delay from
column address to latching first valid read
data.
.
<11:9> S0_RDLYROW RW, 1 Read delay from row address. Delay from
row address to latching first valid read data.
.
<8:7> S0_COLHOLD RW, 1 Column hold (t
CAH
) from b0_cas<1:0>_l
assertion. Used to determine when the
current column address can be changed to
the next column or row address.
.
(continued on next page)
Cache and Memory Subsystem 6–25