User guide

Figure 6–15 Bank 0 Base Address Register: 0x180000800
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LJ-04188.AI
S0_BASEADR<33:23>
MBZ
The base address of each bank must begin on a naturally aligned boundary. For
example, for a bank with 2
n
addresses, the n least significant bits must be zero.
Register bits <4:0> are reserved and must be zero.
6.6.8.4 Configuration Registers
Each memory bank set has a configuration register that contains mode bits,
memory address generation bits, and bank decoding bits. The configuration
registers for banks 0 and 1 have the same format and the same limits for size
and type of DRAMs used. The registers are shown in Figure 6–16 and are defined
in Table 6–6.
Figure 6–16 Configuration Registers for Bank Set 0: 0x180000A00
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LJ-04189.AI
MBZ
S0_COLSEL
S0_SUBENA
S0_SIZE
S0_VALID
6–22 Cache and Memory Subsystem