User guide

Figure 6–13 Presence Detect Low-Data Register: 0x180000280
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04186.AI
PRES_DET<15:0>
6.6.8.2 Presence Detect High-Data Register
After a reset operation, presence detect data are shifted from the memory
configuration and memory ID. The presence detect high-data register stores the
high-order bits of the presence detect data. Bits <15:0> in the register represent
the shifted data bits <31:16>. The register is shown in Figure 6–14.
Note
After reset, the data becomes valid after 148 system clock cycles.
Figure 6–14 Presence Detect High-Data Register: 0x180000260
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04187.AI
PRES_DET<31:16>
6.6.8.3 Base Address Registers
Each memory bank set has a base address register, as shown in Figure 6–15.
The bits in the base address register are compared with the incoming address
sysadr<33:23> to determine which bank is being addressed. The contents of this
register are validated by setting the valid bit in the configuration register of that
bank.
Each bank, which has a minimum size of 2 MB and an 11-bit field, compares bits
<15:5> in the register to sysadr<33:23>.
Cache and Memory Subsystem 6–21