User guide

Figure 6–11 LD x _L Low Address Register: 0x1800000C0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04183.AI
LDXL_LARD<20:5>
6.6.7 LD x _L High Address Register
The LDx_L high address register stores the high-order bits of the latched address.
The register is shown in Figure 6–12. Bits <12:0> represent sysadr<33:21>.
This register is read-only and is not initialized.
Figure 6–12 LD x _L High Address Register: 0x1800000E0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04184.AI
MBZ
LDXL_HARD<33:21>
6.6.8 Memory Control Registers
The registers described in this section control memory configuration and timing.
Each bank of memory has one configuration register, one base register, and two
timing registers. The global timing register and refresh timing register apply to
all banks.
6.6.8.1 Presence Detect Low-Data Register
After a reset operation, presence detect data is shifted from the memory
configuration and memory ID. The presence detect low-data register stores the
low-order bits of the presence detect data. The register is shown in Figure 6–13.
Note
After reset, the data becomes valid after 148 system clock cycles.
6–20 Cache and Memory Subsystem