User guide

Figure 6–9 Error Low Address Register: 0x180000080
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04181.AI
ERR_LADR<20:5>
6.6.5 Error High Address Register
When an error sets the BC_TAPERR, BC_TCPERR, or NXMERR bit in the error
and diagnostic status register, the error high address register latches the high-
order bits of the sysadr<33:21> address that caused the error. If a victim read
caused the error, the victim address is not latched. Instead, the address of the
transaction is latched.
The register is shown in Figure 6–10. Bits <12:0> represent sysadr<33:21>.
Bits <15:13> are reserved and must be zero. This register is read-only. It is not
initialized and is only valid when an error is indicated.
Figure 6–10 Error High Address Register: 0x1800000A0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04182.AI
MBZ
ERR_HADR<33:21>
6.6.6 LD x _L Low Address Register
The LDx_L low address register stores the low-order bits of the last latched
address.
The register is shown in Figure 6–11. Bits <15:0> represent sysadr<20:5>. This
register is read-only and is not initialized.
Cache and Memory Subsystem 6–19