User guide

6.6.3 Tag Enable Register
The tag enable register (TAGEN), shown in Figure 6–8, indicates which bits of
the cache tag are compared to sysadr<33:5>:
• If a bit is 1, the bits in sysadr<33:5> and systag<31:17> are compared. Bits
<15:1> in the register represent systag<31:17>.
• If a bit is 0, no comparison is made, and the systag bit is assumed to be tied
low on the module through a resistor.
This register is not initialized.
Figure 6–8 Tag Enable Register: 0x180000060
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04180.AI
TAGEN<31:17>
MBZ
The upper bits of TAGEN<31:17> are not required to be set. Therefore, an
implementation that does not allow the full 4 GB cacheable memory to be
installed has the option to mask the upper bits of TAGEN<31:17> and so is
not required to store a bit of the tag address in the tag address RAM.
To construct TAGEN<31:17>, refer to Tables 6–4 and 6–5. The value shown in
Table 6–4 (based on the cache size) is ANDed with the value in Table 6–5 (based
on the maximum cacheable system memory). For example, a system with a 16
MB cache, and a maximum of 1 GB cacheable memory would program:
1111 1111 0000 000X
ANDed with
001111111111111X
gives
0011 1111 0000 000X
which is put into TAGEN.
6–16 Cache and Memory Subsystem