User guide

Table 6–2 (Cont.) General Control Register
Field Name Type Description
<5> BC_EN RW, 0 Bcache enable. When clear, the L2 cache is
disabled and the cache state machine does not
probe the cache.
<4> WIDEMEM RO Wide memory size. Reads the status of the
widemem input pin. Returns 1 for the 128-bit
memory interface.
<3> Reserved MBZ —
<2:1> SYSARB RW, 0 DMA arbitration mode. Determines arbitration
scheme for system bus transactions.
Value Meaning
0X CPU priority
10 DMA priority
11 DMA strong priority
<0> Reserved MBZ —
6.6.2 Error and Diagnostic Status Register
The error and diagnostic register contains read-only status information for
diagnostics and error analysis. The register is shown in Figure 6–7 and is defined
in Table 6–3.
When an error occurs, it sets one or more error bits (BC_TAPERR, BC_TCPERR,
NXMERR) and locks the address of the error. After the address is locked, any
additional error sets LOSTERR and does not affect the address or other error
bits. Clearing all of the error bits except the LOSTERR bit unlocks the address.
Cache and Memory Subsystem 6–13