User guide

6.3.2 Memory Address Generation
Each bank has a programmable base address and size. The incoming physical
address is compared with the memory ranges of all banks. The number of bits
that are compared depends on the size of the bank.
The programmable base address of a bank set must be aligned to the natural size
boundary. For example, an 8 MB bank set must start on an 8 MB boundary.
6.3.3 Support for Memory Page Mode
The DECchip 21071-CA supports page mode optimization on the memory banks
within a transaction. Between transactions, page mode is supported on DMA
read burst transactions and on memory write transactions.
6.3.4 Minimizing Read Latency
To minimize the read latency seen by devices on the system bus, the memory
controller optimizes the way it selects transactions. In general, the memory
controller gives priority to read transactions over write transactions because
write transactions can go into a deep write buffer. In some cases, this priority
means the memory controller waits for a read transaction to execute even if there
are write transactions queued in the write buffer.
6.3.5 Transaction Scheduler
The memory interface does memory refresh, cache-line read and write
transactions. The memory controller has a scheduler that prioritizes all
transactions and selects one to be serviced. If the selected transaction is waiting
for row address strobe (RAS) precharge, and another higher priority transaction
is initiated, the scheduler deselects the current transaction and selects the higher
priority transaction.
6.3.6 Programmable Memory Timing
The memory control state machine performs its sequence of steps through all
memory transactions. On memory read and write transactions, it communicates
with the 21071-BA chips so that data may be latched from the memory data
(memData) bus or driven onto the memory data bus, respectively.
The memory control state machine is actually two state machines (master, and
read and write). The master state machine performs the RAS and column address
strobe (CAS) assertions, and controls when the other state machine starts. The
read and write state machine performs the sequencing for generating the memory
command to read or write memory data. The read and write state machine is
started by the master and runs through its sequence independently.
Cache and Memory Subsystem 6–7