User guide

6.2 Bcache Control
Figure 6–4 shows the implementation of a cache subsystem with a 2 MB cache.
Figure 6–4 Cache Subsystem fora2MBCache
ML013276
Bcache SIMMs (2 MB)
Cache/Memory
Control
21071-CA
CPU
128-Bit Data
CPU Cache Control
Tag, Tag V, D, P
Address
System
Cache
Control
Data Path
21071-BA

PAL
Arrays

21071-DA
FCT162244ET
AlphaPC64.10
The Bcache controller provides control for the secondary cache on CPU-initiated
memory read and write transactions that miss, and on all CPU-initiated memory
LDx_L and STx_C transactions (hits and misses).
On DMA-initiated transactions, the Bcache controller probes the cache and
extracts or invalidates the cache line. The 21071-CA supports a write-back cache.
6.3 Memory Controller
This section summarizes memory organization and memory controller features.
Cache and Memory Subsystem 6–5