User guide

6
Cache and Memory Subsystem
The cache and memory subsystem serves as the memory controller and the
system bus (sysBus) controller.
Figure 6–1 Cache and Memory Subsystem
Main
Memory
Data Path
4 chips
Cache and
Memory
Controller
CPU
System Bus (sysBus)
ML013274
Bcache
The components of the cache and memory subsystem are distributed between
the DECchip 21071-CA and the DECchip 21071-BA. Together, the chips are the
interface between the system bus, main memory, and the Bcache (see Figure 6–2).
Cache and Memory Subsystem 6–1