User guide

Table 5–7 PCI Target Address Translation—Direct Mapped
PCI_MASK<31:20> Translated Base <32:5>
0000 0000 0000 T_BASE<32:20>:PCI ad<19:5>
0000 0000 0001 T_BASE<32:21>:PCI ad<20:5>
0000 0000 0011 T_BASE<32:22>:PCI ad<21:5>
0000 0000 0111 T_BASE<32:23>:PCI ad<22:5>
0000 0000 1111 T_BASE<32:24>:PCI ad<23:5>
0000 0001 1111 T_BASE<32:25>:PCI ad<24:5>
0000 0011 1111 T_BASE<32:26>:PCI ad<25:5>
0000 0111 1111 T_BASE<32:27>:PCI ad<26:5>
0000 1111 1111 T_BASE<32:28>:PCI ad<27:5>
0001 1111 1111 T_BASE<32:29>:PCI ad<28:5>
001111111111 T_BASE<32:30>:PCI ad<29:5>
0111 1111 1111 T_BASE<32:31>:PCI ad<30:5>
1111 1111 1111 T_BASE<32>:PCI ad<31:5>
If the SGEN bit is set, the translated address is generated by a table lookup.
The incoming PCI address indexes a table stored in system memory. The table
is referred to as a scatter-gather map. The translated base register specifies the
starting address of the scatter-gather map. Bits of the incoming PCI address are
used as an offset from the base of the map. The map entry provides the physical
address of the page.
Each scatter-gather map entry maps an 8 KB page of PCI address space into
an 8 KB page of processor address space. Each scatter-gather map entry is a
quadword. Each entry has a valid bit in position 0. Address bit ad<13> is at bit
position 1 of the map entry. Because the 21072 implements only valid memory
addresses up to 6 GB, bits ad<63:21> of the scatter-gather map entry must be
programmed to 0. Bits ad<21:1> of the scatter-gather entry generate the physical
page address. This is appended to bits ad<12:5> of the incoming PCI address to
generate the memory address placed on the system bus. Figure 5–5 shows the
scatter-gather map entry.
5–18 System Address Mapping