User guide

Figure 5–3 PCI Memory Space Address Translation
01 000
00
Non-Zero
00000
LJ03938A.AI
Length in Bytes
Longword Address
33 29 2832 31 08 07 0506 04 03 02 00
01
33 32 31 29 28 08 07 0506 04 03 02 00
31
HAXR0
Address Translation for Lower 16M Bytes of PCI Memory Space
Address Translation for Remaining 112M Bytes of PCI Memory Space
27 26 03 02 0001
00
01
31 27 26 00
31 27 26 03 02 00
Byte Offset
Byte Offset
Length in Bytes
Longword Address
HAXR1
Table 5–5 shows the generation of the byte enables and PCI address ad<2:0>
from bits sysBus<6:3>.
Bits sysBus<33:5> are directly available from the CPU. Bits sysBus<4:3> are
derived from the longword masks (cpucwmask<7:0>). On read transactions, the
CPU sends out sysBus<4:3> on cpucwmask<1:0>.
5–12 System Address Mapping