User guide

5.1.8 PCI Sparse Memory Space (0x200000000 to 0x2FFFFFFFF)
Access to PCI sparse memory space can have byte, word, tribyte, longword, or
quadword granularity. The Alpha architecture does not provide byte, word, or
tribyte granularity, which the PCI requires. To provide this granularity, the byte
enable and byte length information is encoded in the lower address bits of this
space (ad<7:3>).
Bits sysBus<31:8> generate quadword addresses on the PCI, resulting in a
sparse 4 GB space that maps to 128 MB of PCI address space. An access to this
space causes a memory read or write access on the PCI.
Bits sysBus<33:32> identify the various address spaces on the system bus.
Bits sysBus<7:3> generate the length of the PCI transaction in bytes, the byte
enables, and ad<2:0> (see Table 5–5). Bits sysBus<31:8> correspond to the
quadword PCI addresses and are sent out on ad<26:3> during the address phase
on the PCI.
Bits ad<31:27> are obtained from one of two host address extension registers
(HAXR0 and HAXR1). HAXR0 (which is hardcoded as 0) is used for system bus
addresses 0x200000000 to 0x21FFFFFFF (that is, when bits sysBus<31:29>
are 0). The HAXR1 register maps system bus addresses 0x220000000 to
0x2FFFFFFFF (that is, when bits sysBus<31:29> are nonzero anywhere in
the PCI address space).
HAXR1 is a CSR in the 21071-DA and is fully programmable. This allows Nbus
devices that require memory to be mapped in the lower 16 MB to coexist with
other devices that do not have that restriction. The lower 16 MB have a fixed
mapping (HAXR0) to 0, and the remaining 112 MB can be programmed anywhere
in PCI space.
Figure 5–3 shows the translation of system bus addresses to PCI memory
addresses. Table 5–5 shows the generation of the byte enables and PCI address
ad<2:0> from bits sysBus<6:3>.
System Address Mapping 5–11