User guide

Peripherals that integrate multiple functional units (for example, SCSI, Ethernet,

and so on) can provide conﬁguration spaces for each function. Bits ad<10:8>,

which are taken from bits sysAdr<15:13>, can be decoded by the peripheral to

select one of eight functional units.

Bits <31:11> are used to generate the IDSEL signals. Typically, the IDSEL# pin

of each PCI peripheral is connected to a unique address line. Bits ad<31:11>, are

decoded from bits sysAdr<20:16> according to Table 5–4, ensuring that only one

bit of ad<31:11> is asserted for any given conﬁguration space transaction on the

primary PCI bus. Bits sysAdr<28:21> are ignored.

5.1.7.2 PCI Conﬁguration Cycles to Secondary Bus Targets

If the PCI cycle is a conﬁguration read or write cycle but bits ad<1:0> are 01, a

device on a secondary PCI bus is being selected across a PCI-to-PCI bridge. This

cycle will be accepted by a PCI-to-PCI bridge for propagation to its secondary PCI

bus. During this cycle, bits sysAdr<28:7> generate PCI ad<23:2>, which has

four ﬁelds, as listed here:

Bits Taken From Operation

ad<23:16> sysAdr<28:21> Select a unique bus number.

ad<15:11> sysAdr<20:16> Select a device on the PCI (typically decoded

by the target bridge to generate IDSEL#

signals).

ad<10:8> sysAdr<15:13> Select one of eight functional units per

device.

ad<7:2> sysAdr<12:7> Select a longword in the device’s conﬁgura-

tion register space.

Each PCI-to-PCI bridge device can be conﬁgured using PCI conﬁguration cycles

on its primary PCI interface. Conﬁguration parameters in the PCI-to-PCI bridge

will identify the bus number for its secondary PCI interface and a range of bus

numbers that may exist hierarchically behind it.

If the bus number of the conﬁguration cycle matches the bus number of the

bridge chip secondary PCI interface, it will intercept the conﬁguration cycle,

decode it, and generate a PCI conﬁguration cycle with ad<1:0> equal to 01

on its secondary PCI interface. If the bus number is within the range of bus

numbers that may exist hierarchically behind its secondary PCI interface, the

PCI conﬁguration cycle passes, unmodiﬁed (leaving ad<1:0> = 01), through the

bridge. The conﬁguration cycle will be intercepted and decoded by a downstream

bridge.

5–10 System Address Mapping