User guide

Table 5–4 PCI Address Decoding for Primary Bus Configuration Accesses
Device Number (sysAdr<20:16>) PCI ad<31:11>
00000 0000 0000 0000 0000 0000 1
00001 0000 0000 0000 0000 0001 0
00010 0000 0000 0000 0000 0010 0
00011 0000 0000 0000 0000 0100 0
00100 0000 0000 0000 0000 1000 0
00101 0000 0000 0000 0001 0000 0
00110 0000 0000 0000 0010 0000 0
00111 0000 0000 0000 0100 0000 0
01000 0000 0000 0000 1000 0000 0
01001 0000 0000 0001 0000 0000 0
01010 0000 0000 0010 0000 0000 0
01011 0000 0000 0100 0000 0000 0
01100 0000 0000 1000 0000 0000 0
01101 0000 0001 0000 0000 0000 0
01110 0000 0010 0000 0000 0000 0
01111 0000 0100 0000 0000 0000 0
10000 0000 1000 0000 0000 0000 0
10001 0001 0000 0000 0000 0000 0
10010 0010 0000 0000 0000 0000 0
10011 0100 0000 0000 0000 0000 0
10100 1000 0000 0000 0000 0000 0
10101 to 11111 0000 0000 0000 0000 0000 0
5.1.7.1 PCI Configuration Cycles to Primary Bus Targets
Primary PCI bus devices are selected during a PCI configuration cycle if:
• Their IDSEL# pin is asserted
• The PCI bus command indicates a configuration read or write transaction
• Bits ad<1:0> are 00
Bits ad<7:2>, which are taken from bits sysAdr<12:7>, select a longword register
in the device’s 256-byte configuration address space. Configuration accesses
can use byte masks, which may be derived by following the method shown in
Table 5–2.
System Address Mapping 5–9