User guide

Table 5–2 PCI Sparse I/O Space Byte Enable Generation
Length
CPU
Address
<6:5>
CPU
Address
<4:3>
PCI Byte
Enable
1
PCI ad<2:0>
Byte 00 00 1110 CPU address<7>,00
01 00 1101 CPU address<7>,01
10 00 1011 CPU address<7>,10
11 00 0111 CPU address<7>,11
Word 00 01 1100 CPU address<7>,00
01 01 1001 CPU address<7>,01
10 01 0011 CPU address<7>,10
11 01 Illegal
2
—
Tribyte 00 10 1000 CPU address<7>,00
01 10 0001 CPU address<7>,01
10 10 Illegal
2
—
11 10 Illegal
2
—
Longword 00 11 0000 CPU address<7>,00
Longword 01 11 Illegal
2
—
Longword 10 11 Illegal
2
—
Quadword 11 11 0000 000
1
Byte enable set to 0 indicates that byte lane carries meaningful data.
2
These combinations are architecturally illegal. If there is an access with this combination of
address<6:3>, the 21071-DA responds to the transactions but the results are UNPREDICTABLE.
Caution
Quadword accesses to this PCI sparse I/O space cause a 2-longword burst
on the PCI. PCI devices cannot support bursting in I/O space.
System Address Mapping 5–7