User guide

Figure 5–2 shows the translation of system bus addresses to PCI bus I/O
addresses. Table 5–2 shows how the byte enable bits and PCI ad<2:0> are
generated from bits sysBus<6:3>.
Figure 5–2 PCI Sparse I/O Space Address Translation
10 1100
000
Non-Zero
00000
00000
LJ03953A.AI
Length in Bytes
sysBus Address
sysBus Address
PCI I/O Address
PCI Memory Space
Byte Offset
33 29 28 23 22 08 07 05 04 03 02 00
10 110
33 29 28 23 22 08 07 05 04 03 02 00
31
HAXR0
Address Translation for Lower 256K Bytes of PCI I/O Space
Address Translation for Remaining 64M bytes - 64K Bytes of PCI Memory Space
24 23 03 02 00
31 24 23 00
31 24 23 03 02 00
Length in Bytes
Byte Offset
HAXR2
5–6 System Address Mapping