User guide

Table 5–1 System Bus Address Space Description
sysAdr
<33:32>
sysAdr
<31:28> Address Space Description
00 xxxx Cacheable memory
space
Accessed by the CPU instruction stream
(Istream) or data stream (Dstream).
Accessed by direct memory access
(DMA).
01 0xxx Noncacheable
memory space
Accessed by the CPU (Istream or
Dstream). Accessed by DMA. Can be
used for a frame buffer on the DRAM
bus.
01 100x 21071-CA CSRs The 21071-CA responds to all addresses
in this space. Dstream access only.
01 1010 21071-DA CSRs The 21071-DA responds to all addresses
in this space. Dstream access only.
01 1011 PCI interrupt
acknowledge or
PCI special cycle
The 21071-CA expects the 21071-DA to
respond to all addresses in this space.
A read transaction causes a PCI
interrupt acknowledge; a write
transaction causes a special cycle.
Dstream access only.
01 110x I/O space 16 MB of PCI space. The lower 256 KB
of this space must be used for addressing
the PCI bus and Nbus devices. The
remainder of the space can be used for
other devices. Dstream access only.
01 111x PCI configuration
space
A read or write transaction to this
address space causes a configuration
read or write cycle on the PCI. Dstream
access only.
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System Address Mapping 5–3