User guide

ManualsBrandsDigital Equipment Corporation ManualsComputer equipmentAlphaPC64

Digital Alpha VME 4/224 and

4/288 Single-Board Computers

User Guide and Technical Description

Order Number: EK–DAVME–TD. B01

This manual describes the Digital Alpha VME 4 module. It provides

conﬁguration and installation procedures and describes the module’s

built-in features, including the console code and diagnostics.

Revision/Update Information: This manual supersedes the Digital

Alpha VME 4/224 and 4/288

Single-Board Computers User

Guide and Technical Description,

EK–DAVME–TD. A01.

Digital Equipment Corporation

Maynard, Massachusetts

Summary of content (442 pages)

PAGE 1
Digital Alpha VME 4/224 and 4/288 Single-Board Computers User Guide and Technical Description Order Number: EK–DAVME–TD. B01 This manual describes the Digital Alpha VME 4 module. It provides configuration and installation procedures and describes the module’s built-in features, including the console code and diagnostics.
PAGE 2
First Printing, July 1996 Revised, September 1996 Printed in U.S.A. The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. FCC Notice: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules.
PAGE 3
Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi 1 Product Overview 1.1 1.2 1.3 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . Physical and Environmental Requirements . . . . . . . . . . . . 1–1 1–1 1–4 2 Installation Procedures 2.1 2.2 2.2.1 2.3 2.4 2.5 2.5.1 2.5.2 2.5.2.1 2.5.2.2 2.5.2.3 2.5.2.4 2.5.2.5 2.5.2.6 2.5.3 2.5.
PAGE 4
3 Operating the Digital Alpha VME 4 Computer 3.1 3.2 3.2.1 3.2.2 3.3 3.4 3.5 Controls and Indicators . . . . . Console Mode . . . . . . . . . . . . . Entering Console Mode . . Exiting Console Mode . . . Environment Variables . . . . . . Booting an Operating System Updating Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
System Address Mapping CPU Address Mapping to PCI Space . . . . . . . . . . . . . Cacheable Memory Space (0x000000000 to 0x0FFFFFFFF) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Noncacheable Memory Space (0x100000000 to 0x17FFFFFFF) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 DECchip 21071-CA CSR Space (0x180000000 to 0x19FFFFFFF) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 DECchip 21071-DA CSR Space (0x1A0000000 to 0x1AFFFFFFF) . . . . . . . . . . . . . . . . . .
PAGE 6
.5 Address Space of Control/Status Registers . . . . . . . . 6.6 Description of CSRs . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1 General Control Register . . . . . . . . . . . . . . . . . . 6.6.2 Error and Diagnostic Status Register . . . . . . . . 6.6.3 Tag Enable Register . . . . . . . . . . . . . . . . . . . . . . 6.6.4 Error Low Address Register . . . . . . . . . . . . . . . . 6.6.5 Error High Address Register . . . . . . . . . . . . . . . 6.6.6 LDx_L Low Address Register . . . . . . . . .
PAGE 7
.3.8 PCI Master Timeout . . . . . . . . . . . . . . . . . 7.3.9 Address Stepping in Configuration Cycles . 7.4 Address Space of Control/Status Registers . . . . 7.5 Description of CSRs . . . . . . . . . . . . . . . . . . . . . 7.5.1 Diagnostic Control/Status Register . . . . . . 7.5.2 PCI Error Address Register . . . . . . . . . . . . 7.5.3 System Bus Error Address Register . . . . . . 7.5.4 Dummy Registers 1 Through 3 . . . . . . . . . 7.5.5 Translated Base Registers 1 and 2 . . . . . . . 7.5.
PAGE 8
9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.3 9.4 9.4.1 9.4.2 9.5 9.6 9.6.1 9.6.2 9.7 9.7.1 9.7.2 9.7.3 9.7.4 9.7.5 9.8 9.9 Module Display Control Register . . . . . . . . . . . . . . . . Module Configuration Register . . . . . . . . . . . . . . . . . . . Interrupt and Interrupt Mask Registers 1, 2, 3, 4 . . . . Memory Configuration Registers 0, 1, 2, 3 and Memory Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . Reset Reason Registers . . . . . . . . . . . . . . . . . . . . .
PAGE 9
Interprocessor Communication . . . . . . . . . . . . . . . . . . . Interprocessor Communication Registers . . . . . . . . Interprocessor Communication Global Switches . . . Interprocessor Communication Module Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 System Controller Operation . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Arbitrating the VMEbus . . . . . . . . . . . . . . . . . . . . . . . 10.3.1.1 Requesting the VMEbus . . . . . . . . . . . . . . . . . . . . .
PAGE 10
11.2 Module Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–13 12 Console Primer 12.1 12.1.1 12.1.2 12.1.3 12.1.4 12.2 12.3 12.4 12.4.1 12.4.2 12.5 12.6 12.7 12.7.1 12.7.2 12.8 12.9 About the Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Console Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Overview . . . . . . . . . . . . . . . . . . . . . . . . . . Shell Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 11
echo . . . . . . . . . eval . . . . . . . . . examine . . . . . exer . . . . . . . . . exit . . . . . . . . . false . . . . . . . . free . . . . . . . . . grep . . . . . . . . . hd . . . . . . . . . . help . . . . . . . . . init_ev . . . . . . . initialize . . . . . kill . . . . . . . . . line . . . . . . . . . ls . . . . . . . . . . . memexer . . . . . memtest . . . . . net . . . . . . . . . ps . . . . . . . . . . pwrup . . . . . . . rm . . . . . . . . . . sa . . . . . . . . . . semaphore . . . . set . . .
PAGE 12
sp . . . start . stop . . update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–100 13–101 13–102 13–103 CPU Connector Pinouts . . . . . . . . . . . . . . . . . . . . .
PAGE 13
2–15 2–16 3–1 4–1 4–2 4–3 4–4 4–5 5–1 5–2 5–3 5–4 5–5 5–6 6–1 6–2 6–3 6–4 6–5 6–6 6–7 6–8 6–9 6–10 6–11 6–12 6–13 6–14 6–15 6–16 6–17 6–18 6–19 Connecting the PMC I/O Companion Card . . . . . . . . . . Installing the PMC I/O Companion Card . . . . . . . . . . . Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . Loopback Descriptions for Interval Timer Test 3 and 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LAN Address ROM Format . . . . . . . . .
PAGE 14
6–20 6–21 7–1 7–2 7–3 7–4 7–5 7–6 7–7 7–8 7–9 7–10 7–11 7–12 7–13 7–14 8–1 8–2 8–3 8–4 9–1 9–2 9–3 9–4 9–5 9–6 9–7 9–8 9–9 9–10 9–11 9–12 9–13 xiv Refresh Timing Register: 0x180000220 . . . . . . . . . . Block Diagram of the DECchip 21071-BA . . . . . . . . PCI Host Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . DECchip 21071-DA Block Diagram . . . . . . . . . . . . . Diagnostic Control/Status Register: 0x1A0000000 . . PCI Error Address Register: 0x1A0000020 . . . . . . .
PAGE 15
9–14 9–15 9–16 9–17 9–18 9–19 9–20 10–1 10–2 10–3 10–4 10–5 10–6 10–7 10–8 10–9 10–10 10–11 10–12 10–13 10–14 10–15 10–16 10–17 10–18 11–1 11–2 11–3 11–4 11–5 11–6 11–7 11–8 11–9 11–10 82C54 Timer Data Access . . . . . . . . . . . . . . . . . . Timer Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Interrupt Status Register . . . . . . . . . . . . . Watchdog Timer Registers . . . . . . . . . . . . . . . . . . Watchdog Timer TOY Clock Command Register .
PAGE 16
11–11 11–12 11–13 11–14 A–1 A–2 A–3 A–4 A–5 A–6 A–7 VIC Error Group ICR . . . . . . . . . . . . . . . . . . . . . . . . . VMEbus Interrupter ICR . . . . . . . . . . . . . . . . . . . . . . VIC Error Group Interrupt Vector Base Register . . . . NMI Status and Control Register . . . . . . . . . . . . . . . Console (J6) and Serial (J7) Connector Pinouts . . . . . Ethernet (J9) Connector Pinouts . . . . . . . . . . . . . . . . Primary Breakout Module Connector Pinouts . . . . . .
PAGE 17
3–1 3–2 4–1 5–1 5–2 5–3 5–4 5–5 5–6 5–7 5–8 6–1 6–2 6–3 6–4 6–5 6–6 6–7 6–8 6–9 6–10 7–1 7–2 7–3 7–4 7–5 7–6 7–7 7–8 7–9 7–10 7–11 7–12 8–1 8–2 9–1 Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . Environment Variable Summary . . . . . . . . . . . . . . . . . Console Diagnostic Tests . . . . . . . . . . . . . . . . . . . . . . . System Bus Address Space Description . . . . . . . . . . . . PCI Sparse I/O Space Byte Enable Generation . . . . . . PCI Configuration Space Definition . . .
PAGE 18
9–2 9–3 9–4 9–5 9–6 9–7 9–8 9–9 9–10 9–11 9–12 9–13 9–14 9–15 9–16 9–17 9–18 9–19 10–1 10–2 10–3 10–4 10–5 10–6 10–7 10–8 10–9 10–10 10–11 10–12 10–13 10–14 10–15 10–16 xviii Module Configuration Register . . . . . . . . . . . . . . . . . . . DIMM Identification . . . . . . . . . . . . . . . . . . . . . . . . . . Presence Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory DIMM Configuration Bit . . . .
PAGE 19
11–1 11–2 11–3 11–4 12–1 12–2 12–3 A–1 A–2 A–3 A–4 A–5 A–6 A–7 A–8 Table of CPU Interrupt Assignments . . . . . . . . . . . . VIC64 Chip Interrupt Ranking . . . . . . . . . . . . . . . . VME IRQ ICR Priority Assignments . . . . . . . . . . . . NMI Status and Control Register Bits . . . . . . . . . . . Commonly Used Commands . . . . . . . . . . . . . . . . . . . Console Shell Operators . . . . . . . . . . . . . . . . . . . . . Digital Alpha VME 4 Console Command Summary .....................................
PAGE 20
PAGE 21
Preface Purpose of this Manual This manual describes the Digital Alpha VME 4 module. It provides configuration and installation procedures and describes the module’s built-in features, including the console code and diagnostics. Intended Audience This manual is for OEM system integrators who have extensive knowledge of single-board computers (SBCs). Their task is to integrate Digital Alpha VME 4 modules into their own systems.
PAGE 22
• Chapter 3, Operating the Digital Alpha VME 4 Computer, explains how to use the Digital Alpha VME 4 module’s controls and indicators, introduces console mode and environment variables, and provides pointers to information on booting operating systems and updating firmware. • Chapter 4, Diagnostics, describes the Digital Alpha VME 4 power-on self-test (POST) diagnostics and ROM based diagnostics (RBDs).
PAGE 23
Conventions This section defines terminology, abbreviations, and other conventions used in this manual. Abbreviations • Register access The following list describes the register bit and field abbreviations: • Bit/Field Abbreviation Description MBZ (must be zero) Bits and fields specified as MBZ must be zero. RO (read only) Bits and fields specified as RO can be read but not written. RW (read/write) Bits and fields specified as RW can be read and written.
PAGE 24
Caution Cautions indicate potential damage to equipment or loss of data. Data Field Size The term INTnn, where nn is one of 2, 4, 8, 16, 32, or 64, refers to a data field of nn contiguous NATURALLY ALIGNED bytes. For example, INT4 refers to a NATURALLY ALIGNED longword. Data Units The following data unit terminology is used throughout this manual.
PAGE 25
Names and Symbols The following table lists typographical conventions used for names of various items throughout this manual.
PAGE 26
Syntax The following syntax elements are used throughout this manual. Do not type the syntax elements when entering information. Element Example Description [] [-file filename] The enclosed items are optional. | - | + | = Choose one of two or more items. Select one of the items unless the items are optional. {} {- | + | =} You must specify one (and only one) of the enclosed items. () — You must specify the enclosed items together. arg . . .
PAGE 27
Operations that produce UNPREDICTABLE results might also produce exceptions. An occurrence specifed as UNPREDICTABLE might happen or not based on an arbitrary choice function. The choice function is subject to the same constraints as are UNPREDICTABLE results and, in particular, must not constitute a security hole.
PAGE 28
For More Information Document Order Number CY7C9640 Specification Company Cypress Semiconductor Corp. DECchip 21040–AA Specification EC–N0752–72 Digital Equipment Corp. DECchip 21064–AA Microprocessor Hardware Reference Manual EC–N0079–72 Digital Equipment Corp. DECchip 21072–AA Core Logic Chip Set EC–N0648–72 Digital Equipment Corp. Digital UNIX Installation Guide AA–PS2DD–TE Digital Equipment Corp. Intel SIO82378 Chip Specification Intel Corp.
PAGE 29
1 Product Overview 1.1 Product Description The Digital Alpha VME 4/224 and 4/288 MHz single-board computers are based on the 21064A Alpha processor chip. The Digital Alpha VME 4/224 comes preconfigured with 512 KB cache, and the Digital Alpha VME 4/288 comes preconfigured with 2 MB cache.
PAGE 30
Table 1–1 Digital Alpha VME 4 Functional Specifications Item Description Alpha AXP processor 21064A Alpha processor with on-chip 16 KB instruction and 16 KB data caches IEEE and VAX floating point. Peformance At 288 MHz, 238.51 SPECfp92, 188.84 SPECint92, 5.44 SPECfp95, and 4.69 SPECint95. Network features DECchip 21040 PCI Ethernet controller DMA (bus master), 256 byte send and receive FIFO, double bandwidth with full duplex Ethernet (PCI based).
PAGE 31
Figure 1–1 Digital Alpha VME 4 Block Diagram Cache and Memory Controller CPU 128 memdata 64 Bcache CPU Board Data Path 4 chips sysBus 128 Bits PCI Host Bridge (21071-DA) Main Memory 32 epiData (DS1386) I/O Board TOY Clock Interrupt Controller PCI to Nbus Bridge Flash Watchdog Timer NVRAM Nbus 8 Bits Keyboard and Mouse Controller Super I/O Interval Timer PCI Bus 32 Bits PCI-VME Bridge SCSI Controller Ethernet Controller PCI to PCI Bridge PCI/PMC option 0 slot VME Connectors PCI/PMC opti
PAGE 32
1.3 Physical and Environmental Requirements The Digital Alpha VME 4 module requires a VME chassis with sufficient cooling. You must have at least 200 linear feet/minute (lfm) of airflow at an ambient temperature of not more than 40°C (104°F) across the processor heatsink. Table 1–2 shows the physical and environmental specifications for the Digital Alpha VME 4 module. Table 1–3 shows the power supply current and power dissipation for the Digital Alpha VME 4 module.
PAGE 33
Table 1–3 Typical Peak Power Supply Current and Module Power Dissipation CPU Modules w/128 MB Memory Amps @5V Amps @ 12 V (note 1) Amps @012 V Module Heat Dissipation Alpha VME 4/224 12.0 A 0.2 A 0.01 A 62 W Alpha VME 4/288 13.5 A 0.2 A 0.01 A 70 W Options Amps @5V Amps @ 12 V Amps @012 V Power Dissipation SCSI Termination 0.8 A max. 0.0 A N/A 4 W max. PMC Option Slot Budget 3.0 A max. N/A N/A 15 W max. Notes Power and heat dissipation assumes nominal voltages (5.0 V, 12.
PAGE 34
PAGE 35
2 Installation Procedures This chapter describes how to unpack, configure, install, and verify proper operation of the Digital Alpha VME 4 module. 2.1 Unpacking Your Digital Alpha VME 4 hardware kit contains the items listed in Table 2–1. Save the original packing material in case a factory return is necessary. Caution You must install the primary breakout module (54-24663-01) included in your hardware kit (see Figure 2–7).
PAGE 36
Figure 2–1 Digital Alpha VME 4 Module Components 1 2 3 4 7 5 ! " # $ % & ' 6 MLO-013240 Optional PMC I/O companion card I/O module Digital Alpha VME 4 module Memory modules Cache memory modules Secondary breakout module Primary breakout module Table 2–1 lists Digital Alpha VME 4 hardware kit items. The kits in Table 2–1 contain hardware only. The option you receive may also include software licenses or software, depending on what is ordered.
PAGE 37
Table 2–1 Digital Alpha VME 4 Hardware Kit Items Item Part Number Digital Alpha VME 4/224 Kit Digital Alpha VME 4 module I/O assembly Digital Alpha VME 4 Primary breakout module 70–32976–04 (includes 512 KB cache) (54–24325–04 + 54–24319–01) 1 54–24663–01 Digital Alpha VME 4 Secondary breakout module 54–24729–01 Alpha VME 4/228 and 4/288 Single-Board Computers User’s Guide and Technical Description EK–DAVME–TD Antistatic wriststrap 12–36175–01 Digital Alpha VME 4/288 Kit Digital Alpha VME 4 modul
PAGE 38
Table 2–2 Digital Alpha VME 4 Memory Modules Memory Size (MB) Kit Number Part Number 16 EBMXM-DB 54–24659–AB 32 EBMXM-EB 54–24659–AA 64 EBMXM-FB 54–24645–AA Table 2–3 Digital Alpha VME 4 Cache Memory Modules Memory Size Kit Number Part Number Quantity 512 KB EBMXC–BA 54–24685–AA 2 2 MB EBMXC–DB 54–24683–AA 2 Depending on how you plan to use the Digital Alpha VME 4 system, you may need one or more of the items listed in Table 2–4 that are not part of the Digital Alpha VME 4 kit.
PAGE 39
Table 2–4 Additional Hardware Installation Items Item Supplier Part Number Serial line cable for console and auxiliary terminals Digital BC16E– nn1 IEEE 802.3 Twisted-pair transceiver to ThinWire Digital DETTR–AA IEEE 802.3 Twisted-pair transceiver to twistedpair Digital DETTR–BB 10BASET loopback connector Digital 12-35619-01 (H4082-AA) SCSI 20.32 cm (8 in), 30.48 cm (12 in), or 53.
PAGE 40
2.2 Installation To install the Digital Alpha VME 4 module, perform the following steps: 1. Select two adjacent slots in your VME backplane for the Digital Alpha VME 4 module. If you are installing a PMC I/O companion card, you will need to select three adjacent slots. Refer to Section 2.2.1 for instructions on how to install the PMC I/O companion card. Caution Static electricity can destroy the circuits on the modules in your Digital Alpha VME 4 kit.
PAGE 41
Figure 2–2 Digital Alpha VME 4 Module Layout 8 9 7 1 2 MB C B A 2 6 512 KB 5 4 3 512 KB C B A D C B A 2 MB D C B A MLO-013237 ! " # $ % & ' ( ) Cache memory connectors Memory connectors Cache configuration select jumper (J9) Power and VME slave activity/watchdog timeout LEDs Status display Cache memory size and speed select jumper (J10) I/O module connector VME connectors SROM (8 pin) Installation Procedures 2–7
PAGE 42
Figure 2–3 I/O Module Layout 5 6 7 OPEN OFF 4 9 3 2 1 ON 8 10 4 ! " # $ % & ' ( ) +> 3 1 2 MLO-013238 Console serial port Auxiliary serial port Reset/halt switch Twisted pair Ethernet connector Connector to CPU module (on back of I/O module) Debug jumper (not installed for normal operation) Configuration switchpack PMC I/O companion card connector Ethernet Address ROM NVRAM/TOY clock 2–8 Installation Procedures
PAGE 43
2. Set the configuration switches on the I/O module as outlined in Table 2–5, Table 2–6, and Table 2–7. Also refer to Figure 2–3 for the configuration switch location. Table 2–5 Digital Alpha VME 4 Module Configuration Switches Switch Setting Function 1 Closed Supplies +5 V from the VMEbus +5 V Standby signal to the timeof-year (TOY) clock and the nonvolatile random-access memory (NVRAM) to supplement the internal battery when the Digital Alpha VME 4 module is turned off.
PAGE 44
Table 2–7 Supported Switch Settings for Digital Alpha VME 4 Modules in Other Than Slot 1 (Nonsystem Controller) Switch Setting 1 Closed 2 Open 3 Closed1 4 Open1 1 These switches are required to be in the indicated positions (one opened, one closed) for reliable system operation during a VMEbus Reset. 3. Install the memory module on your Digital Alpha VME 4 module (Figure 2–4) in the following manner: • Populate bank 0 first, then bank 1, if necessary.
PAGE 45
Figure 2–4 Installing the Main Memory Modules 1 2 4 3 MLO-013246 ! " # $ Memory bank 0 slots A and B Memory bank 1 slots A and B Orientation notches Memory connector Table 2–8 shows all possible valid memory configurations.
PAGE 46
Table 2–8 Digital Alpha VME 4 Memory Configurations Memory Size (MB) Bank 0 Slot A Bank 0 Slot B Bank 1 Slot A Bank 1 Slot B 16 8 8 32 8 8 32 16 16 8 8 48 8 8 16 16 64 16 16 16 16 64 32 32 96 16 16 32 32 96 32 32 16 16 128 32 32 32 32 4. Cache memory DIMMs are installed on your Digital Alpha VME 4 module by Digital. Pin 1 of the DIMM is aligned with pin 1 on the cache connector.
PAGE 47
Figure 2–5 Cache Memory Modules 1 2 MLO-013245 ! " Orientation notch Cache memory connector 5. The J9 and J10 jumpers are preconfigured for your Digital Alpha VME 4 module by Digital. Table 2–9, Table 2–10, and Figure 2–2 show jumper settings and locations for informational purposes only.
PAGE 48
Table 2–10 J10 Cache Jumper Settings A B C Total Size In In In Disable cache In In Out Reserved In Out In 2 MB In Out Out Reserved Out In In 512 KB Out In Out Reserved Out Out In Reserved Out Out Out Reserved Speed 12 ns 15 ns Note If you are installing the PMC I/O companion card, proceed to Section 2.2.1 later in this chapter and complete the installation instructions before continuing on to step 6. 6.
PAGE 49
Figure 2–6 Installing the Digital Alpha VME 4 Module 1 MLO-013236 Caution You must install the primary breakout module (54-24663-01) included in your hardware kit (see Figure 2–7). Applying power to the Digital Alpha VME 4 module WITHOUT that primary breakout module in place, or WITH the breakout module included with the AXPvme 160, 166, or 230 (P/N 54–22605–01) in place may damage your backplane, the Digital Alpha VME 4 module, or both. Also, do not press on the LED window when you install the module.
PAGE 50
2 4 6 3 5 ! 1 Figure 2–7 Alpha VME 4 Primary Breakout Module Part Number: 54-24663-01 Part Number: 54-22605-01 MLO-013263 7. Set the SCSI termination jumper on the breakout module (refer to Figure 2–8). The SCSI bus must be terminated at each end. In most installations, the breakout module is one end of the SCSI bus and the far end of the SCSI ribbon cable is the other end of the SCSI bus. In this case, enable the SCSI termination by placing the jumper across pins 1 and 3 (default).
PAGE 51
component. The monitoring device must also be connected to the same ground reference as the Digital Alpha VME 4 module. The external watchdog reset signal is on pin C10 of the VMEbus J3 (P2) connector on the breakout module. This signal is low during normal operation and high during a watchdog timer reset (provided that pullup power is connected).
PAGE 52
Figure 2–9 Connecting the SCSI Cable to the Primary Breakout Module MLO-013241 10. Install the primary breakout module (refer to Figure 2–10). Ensure that the breakout module is installed behind the slots occupied by the Digital Alpha VME 4 module (as shown). Caution Running the Digital Alpha VME 4 module when it is not in the same slots as the correct breakout module (refer to Figure 2–10) may damage your backplane, the Digital Alpha VME 4 module, or both.
PAGE 53
Figure 2–10 Installing the Primary Breakout Module MLO-013264 11. A secondary breakout module is included in the hardware kit, which you can connect to the primary breakout module. If you use the secondary breakout module, set the jumpers on that module as shown in Figure 2–11. Note An incremental clearance of at least 56.25 mm (2.25 inches) is required to install the secondary breakout module.
PAGE 54
Figure 2–11 Secondary Breakout Module Jumpers Keyboard / Mouse Disabled 3 Keyboard / Mouse Enabled 3 1 3 1 3 1 3 1 4 2 4 2 4 2 4 2 2 1 4 MLO-013353 ! " # $ Mouse and keyboard connector Mouse and keyboard Y cable (17-04230-01) Keyboard and mouse jumper configurations Parallel port (see Appendix A for pinouts) 12. Connect the secondary breakout module to the primary breakout module as shown in Figure 2–12.
PAGE 55
Figure 2–12 Connecting the Secondary Breakout Module to the Primary Breakout Module 1 2 MLO-013266 ! " Primary breakout module (54-24663-01) Secondary breakout module (54-24729-01) 13. Connect the network cable (if any) to the twisted-pair Ethernet connector. See Figure 2–13. Associated with the Ethernet connector are devices to convert from twisted pair to ThinWire (P/N DETTR–AA). See Table 2–4. 14. Connect the console terminal cable to the Digital Alpha VME 4 module (refer to Figure 2–13). 15.
PAGE 56
Figure 2–13 Connecting Network and Console Terminal Cables 1 2 3 MLO-013352 ! " # Network Console Auxiliary 16. Insert blank panels into the vacant slots of the VME chassis. This improves airflow and reduces electromagnetic interference (EMI) radiation. 17. Your installation is complete and power can be turned on. 18. When you turn power on, the Power LED lights (refer to Figure 3–1) and the Digital Alpha VME 4 module runs its power-up self-test display (POST). This takes about 30 seconds.
PAGE 57
2.2.1 Installing the PMC I/O Companion Card Figure 2–14 shows the layout of the PMC I/O companion card. Note To install the PMC I/O companion card with the Digital Alpha VME 4, you must have three adjacent slots available. Figure 2–14 PMC I/O Companion Card Layout 9 10 7 3.3 V 5.
PAGE 58
' ( ) +> Signaling level jumper (jumper MUST be set to 5.0 V) PMC option slots VME connectors I/O-to-P2 signal connector Caution Perform the following steps gently to avoid damage to the modules. 1. Make sure the signaling-level jumper on the PMC I/O companion card is set for 5.0 V, as show in Figure 2–14. 2. Install any user-supplied PMC options. 3.
PAGE 59
seating the Alpha VME module in the VME chassis. If you do not retract the screws completely: • The Alpha VME module might not seat properly. • The press-fit shoulder washer that holds the screw washer in place might become disengaged if you apply excessive pressure to the front panel. 7. Tighten the six screws on the handles as shown in Figure 2–16. 8. If being used, connect the mouse and keyboard cables at the locations shown in Figure 2–14.
PAGE 60
Figure 2–15 Connecting the PMC I/O Companion Card MLO-013265 2–26 Installation Procedures
PAGE 61
Figure 2–16 Installing the PMC I/O Companion Card 1 MLO-013411 9. Return to step 6 in Section 2.2 for instructions on installing the Digital Alpha VME 4 module into the VME chassis and setting up and installing the breakout modules. 2.3 Diagnostics When you turn on the power or toggle the Reset switch, the Digital Alpha VME 4 module runs its POST. The module runs a series of tests stored in the serial read-only memory (SROM) and then runs a series of console code tests stored in the flash ROMs.
PAGE 62
Table 2–11 SROM Test Numbers and Descriptions LED Display COM1 Meaning 8 - Nbus bus has been reset and SIO configured. 7 7.. COM1 port has been initialized (9600 baud). 6 6.. BIU_CTL register has been programmed according to the cache configuration jumpers, but Bcache is not on line. 5 5.. Main memory DIMMs have been configured according to PD bits. Memory is alive but not scrubbed. 4 4.. Bcache has been initialized and put on line. 3 3..
PAGE 63
Table 2–12 Console Code Test Letters and Names Test Letter Test Name A SCSI control and status register (CSR) test B Heartbeat timer test C Interval timer test D DS1386 nonvolatile RAM tests E Auxiliary Universal Asynchronous Receiver/Transmitter (UART) test F Ethernet address ROM test G Ethernet internal and external loopback tests H Watchdog timer test I VME interface processor/VIC64 test After the POST completes and the system is idle, the console outputs a ‘‘rotating bar’’ to the LED
PAGE 64
If all SROM and flash ROM-based diagnostics pass, and an auto_action1 boot command has been set, the >>> console prompt appears on the console terminal and the dot matrix display will display a ‘‘rotating bar.’’ Note that a problem in the PMC I/O companion card that hangs the PCI bus signal lines could cause diagnostics to report problems throughout the I/O subsystem and in the PCI controller of the processor chip.
PAGE 65
Table 2–13 Troubleshooting Symptom Corrective Action No LEDs lit, no console prompts. Check power. If 5 V power is out of specification, the module will be held in reset. Green LED on, blank dot matrix display, and no console prompts Check the seating of SROM (8-pin socketed device near PCI port). See Figure 2–2. Green LED on, dot matrix displays the number 5 on power-up. Check the seating of the memory modules. Green LED on, dot matrix displays the number 0 on power-up.
PAGE 66
2.5 Repair and Warranty Information 2.5.
PAGE 67
2.5.2.2 Return-to-Digital Process To return products under warranty, contact the Digital Customer Support Center in your particular geography. The Customer Support Center provides you with a Return Material Authorization (RMA#) and an address to which to send the defective material. You are responsible for sending the product to the address provided and for prepaying transportation costs associated with returning the product to the nearest Digital return center.
PAGE 68
• Assume all risk of loss or damage to field replaceable units in transit to Digital. 2.5.2.6 Pre-Call Checklist To allow Digital to assist you quickly and efficiently, consult the following checklist before calling Digital or your authorized reseller: 1. Consult your product user documentation to assure that your system features are properly configured. 2. Execute the customer diagnostics provided with the product, if applicable, and record the information. 3.
PAGE 69
2.5.4 Field Replaceable Units and Order Numbers Table 2–15 lists the available field replacable units and their associated order numbers.
PAGE 70
PAGE 71
3 Operating the Digital Alpha VME 4 Computer 3.1 Controls and Indicators Figure 3–1 shows the front panel controls and indicators of the Digital Alpha VME 4 module and Table 3–1 describes their function.
PAGE 72
Figure 3–1 Controls and Indicators 1 2 3 4 MLO-013262 Table 3–1 Controls and Indicators ! Control or Indicator Description Reset/Halt switch " A switch that resets the Digital Alpha VME 4 system when pressed in the Reset (up) direction. When pressed in the Halt (down) direction this switch halts the operating system and the module enters console mode. Status display A display that shows which test is running during the POST.
PAGE 73
3.2 Console Mode Sections 3.2.1 and 3.2.2 explain how a Digital Alpha VME 4 system enters and exits console mode. 3.2.1 Entering Console Mode A Digital Alpha VME 4 module enters console mode automatically when the POST is finished. A Digital Alpha VME 4 module also enters console mode when: • You press the Reset/Halt switch on the front panel. Caution Depending on the operating system and applications running at the time, this could damage application files that are open and have not been saved.
PAGE 74
Note Do not change the settings of the environment variables without understanding the implications of the changes. Table 3–2 lists the environment variables with descriptions. Table 3–2 Environment Variable Summary Variable Description AUTO_ACTION Defines the action of the console following an error, halt, or power-up. BOOT_DEV Specifies the device list to be used by the last, or currently in progress, bootstrap attempt.
PAGE 75
Table 3–2 (Cont.) Environment Variable Summary Variable Description D_EOP Specifies whether end-of-pass messages are to be displayed. D_GROUP Specifies the diagnostic group to be executed. D_HARDERR Defines the action that is to be taken following a hard error detection. D_OPER Specifies whether an operator is present. D_PASSES Specifies the diagnostic pass count. D_REPORT Specifies the level of information to be provided by diagnostic error reports.
PAGE 76
Table 3–2 (Cont.) Environment Variable Summary Variable Description EWA0_DEF_SINETADDR Specifies the initial value for EWA0_SINETADDR when the interface’s internal Internet database is initialized from BOOTP (EWA0_INET_INIT is set to BOOTP). EWA0_INET_INIT Specifies whether the interface’s internal Internet database is to be initialized from non-volatile RAM (NVRAM) or from a network server (by way of BOOTP). EWA0_LOOP_COUNT Specifies the number of times each message is looped.
PAGE 77
Table 3–2 (Cont.) Environment Variable Summary Variable Description VME_A32_BASE Specifies the base address of VMEbus A32 space. VME_A32_SIZE Specifies the size of VMEbus A32 space. VME_A24_BASE Specifies the base address of VMEbus A24 space. VME_A24_SIZE Specifies the size of VMEbus A24 space. VME_A16_BASE Specifies the base address of VMEbus A16 space. VME_CONFIG Specifies the VME setup mode. VX_BOOTLINE Specifies the name of the file to be used for the VxWorks bootstrap. 3.
PAGE 78
PAGE 79
4 Diagnostics 4.1 Overview This chapter describes the Digital Alpha VME 4 power-on self-test (POST) diagnostics and additional ROM-based diagnostics (RBDs). Diagnostics for the Digital Alpha VME 4 system provide a fast, high coverage suite of POSTs to be invoked automatically at power-on and system reset. In addition to the POSTs, there are RBDs that provide additional testing and fault isolation. You invoke RBDs at the console prompt from the console terminal.
PAGE 80
Failures detected by the SROM-based tests are indicated by the test sequence halting and the LED display permanently showing the failing test number. A detailed dump of internal registers, program counter, expected and actual data is performed either through the serial port of the 21064 or through the console Universal Asynchronous Receiver/Transmitter (UART).
PAGE 81
Table 4–1 Console Diagnostic Tests HW Under Test Command Memory and Cache - Memory exerciser test memtest or mem_ex Network Interface - DECchip 21040 network interface internal loopback test niil_diag -t 1 - DECchip 21040 network interface external loopback test niil_diag -t 2 - DECchip 21040 network interface control /status register (CSR) test nicsr_diag -t 1 - DECchip 21040 network interface CSR test nicsr_diag -t 2 - DECchip 21040 network interface CSR test nicsr_diag -t 3 NVRAM + TOY Cloc
PAGE 82
Table 4–1 (Cont.) Console Diagnostic Tests HW Under Test Command - SCSI device exer exer dk Timers - Heartbeat timer test hbeat_diag -t 1 - Interval timer test i8254 -t 1 - Interval timer test i8254 -t 2 - Interval timer test i8254 -t 3* - Interval timer test i8254 -t 4* - Interval timer test i8254 -t 5 - Interval timer test i8254 -t 6 - Watchdog timer test wdog_diag -t 1 * Requires external loopback connector configured as shown in Figure 4–1.
PAGE 83
LED Display Output on Console Meaning 8 – Nbus bus has been reset and system I/O (SIO) configured. 7 7.. COM1 port has been initialized (9600 baud). 6 6.. BIU_CTL register has been programmed according to the cache configuration jumpers, but Bcache was not enabled. 5 5.. Main memory controller has been configured according to the DIMM PD/ID bits. Memory is alive but was not scrubbed. 4 4.. Bcache has been initialized and enabled. 3 3..
PAGE 84
POST Non-Volatile RAM Diagnostic POST Non-Volatile RAM Diagnostic The POST Non-Volatile RAM (NVRAM) diagnostic test verifies the module’s NVRAM. It performs a data integrity test, through power cycles, and a write /read/compare of specific NVRAM locations used for diagnostics. It also checks for uninitialized NVRAM by comparing the stored checksum with the calculated checksum. Description This test executes at the beginning of console boot before the console drivers and devices have been initialized.
PAGE 85
POST Memory Diagnostic POST Memory Diagnostic The POST memory diagnostic test verifies system memory. It runs with ECC enabled. If the test detects a memory error that cannot be corrected with ECC, it logs the error in the error logging area of NVRAM. Description See also memtest in Chapter 13. Note This test is dependent upon the setting of the console MODE environment variable. Setting mode to FASTBOOT evokes a quick verify test of the memory, and NOFASTBOOT evokes a full test of memory.
PAGE 86
4.3.4 Console Diagnostic Test Descriptions This section provides details on the tests, which are available to the console, that you might run during system initialization testing or run from the console.
PAGE 87
Heartbeat Timer Test Heartbeat Timer Test The heartbeat timer diagnostic test verifies that a heartbeat interrupt is generated at the correct interval (1024 Hz) and is properly dismissed by way of the module clear heartbeat register. This test checks the following logic: • Heartbeat timer and interrupt delivery mechanism • Module clear heartbeat register Heartbeat Timer Test Console Command: hbeat_diag -t 1 Command Option: -dd: print detailed test information on each pass.
PAGE 88
Interval Timer Tests Interval Timer Tests The interval timer tests test the functionality of the 8254 interval timer chip and surrounding external circuitry, including latches, programmable-array logic (PAL) devices and printed circuit board module etch. Since all three interval timers of the 8254 chip have different external configurations, several tests are required for complete test coverage.
PAGE 89
Interval Timer Tests • See the Intel 8254 interval timer sheet for more details. Timer 2 Square Wave Test This test exercises timer 2. In the Digital Alpha VME 4 design, the gate input for timer 2 is always enabled and the clock input is connected to a 10 MHz (100 ns period) clock source. Timer 2 is programmed to mode 3, square wave mode.
PAGE 90
Interval Timer Tests This test essentially emulates the realtime time provider and slave scheme found in the Realtime Clock and Interval Device Driver functional specification. Note A VMEbus P2 loopback connector is required. See Figure 4–1 for a description of the loopback connections. Using the -lp option enables the timers indefinitely, making the module the master time provider for test #4. Timer 2 and timer 1 are programmed to mode 3, square wave mode. Timer 0 is programmed to mode 1.
PAGE 91
Interval Timer Tests This test enables only timer 0 as done in test 3 but does not use timer 1 or timer 2. The clock and gate come from the timers on the master Digital Alpha VME 4 module. Timer 0 interrupts when the gate is received and its count is decremented to 0. Note A VMEbus P2 loopback connector is required. See Figure 4–1 for a description of the loopback connections.
PAGE 92
Interval Timer Tests • Due to hardware limitations on interrupt detection, the value programmed into timer 2 must be greater than 2. • See the Intel 8254 interval timer sheet for more details. Timer 1 Interrupt Test This test verifies the interrupt path of timer 1 (periodic RT timer). Timer 1 is programmed to mode 3, square wave mode. After the timer is initially programmed to mode 3 and loaded with a count value, the OUT output is low and remains low until the internal count value reaches zero.
PAGE 93
Interval Timer Tests Figure 4–1 Loopback Descriptions for Interval Timer Test 3 and 4 Configuration for Interval Timer test 3 To make a loopback for test 3 connect pin C11 to C14. With a second jumper, connect C12 to C13. (VMEbus P2 Connector) row C B A 14 13 12 11 Configuration for Interval Timer test 4 (MASTER/SLAVE Alpha VME) For test 4, the MASTER signals must be the input for the second Alpha VME module. Connect pins C11 and C14 of the MASTER to C14 of the SLAVE.
PAGE 94
DECchip 21040 Ethernet Controller Tests DECchip 21040 Ethernet Controller Tests These diagnostics verify that the internal and external loopback mechanisms are properly operating in the DECchip 21040 Ethernet controller chip as well as performing writes and reads to all configuration registers. Ethernet Internal Loopback Test The NI internal loopback test transmits Ethernet packets from the transmit ring in main memory, loops them back at the MAC layer and returns them to the receive ring in main memory.
PAGE 95
DECchip 21040 Ethernet Controller Tests DECchip 21040 PCI Configuration Register Dump This test reads the PCI configuration registers of the DECchip 21040 and prints them to the standard output. Console Command: nicsr_diag -t 1 DECchip 21040 Control/Status Register Dump This test reads the CSRs of the DECchip 21040 and prints them to the standard output.
PAGE 96
DALLAS DS1386 RAMified Watchdog Timekeeper Tests DALLAS DS1386 RAMified Watchdog Timekeeper Tests The DS1386 consists of 32 KB of NVRAM and a realtime clock. This diagnostic tests each of these features on an individual basis. The diagnostic tests the DS1386, decoders, and printed circuit board module etch. The functionality of the watchdog feature is to be tested in a separate diagnostic. No alarm features are tested, since the alarms are not used. Tests 1 through 3 exercise the NVRAM.
PAGE 97
DALLAS DS1386 RAMified Watchdog Timekeeper Tests NVRAM Address-On-Address Test The NVRAM locations in the DS1386 are byte wide. Therefore, you do not have enough room to write the unique address into each corresponding location. However, this test writes the unique page offset to its corresponding location in NVRAM. This test writes, reads, and compares all 32 KB of NVRAM using this unique page offset for test data. If the quick verify option is set (default) only the first location of each page is tested.
PAGE 98
DALLAS DS1386 RAMified Watchdog Timekeeper Tests Console Command: ds1386_diag -t 3 Command Options: • -dd: print detailed test information on each pass. • -nqv: test every location in NVRAM, default is to test 1 location per 256 byte page. Miscellaneous Note This diagnostic is an extended test. TOY Clock Bitwalk Test This diagnostic does a walking 1, walking 0, and A5 register test on the time-ofyear (TOY) clock registers. It also tests the rollover cases associated with keeping time.
PAGE 99
DALLAS DS1386 RAMified Watchdog Timekeeper Tests Console Command: ds1386_diag -t 4 Command Option: -dd: print detailed test information on each pass. Miscellaneous Note This diagnostic is an extended test. TOY Clock Time Advancement Test This diagnostic is a power-on diagnostic. It verifies that the TOY clock registers are advancing with clock ticks. The test reads the current value of the seconds register. Then the test sleeps for 1.
PAGE 100
Local Area Network Address ROM Test Local Area Network Address ROM Test This diagnostic tests the integrity of the Local Area Network (LAN) address ROM, decoders, and printed circuit board module etch. The LAN address ROM contains the Ethernet station address of the module. LAN Address ROM Dump This diagnostic dumps the contents of the 32 octets within the LAN address ROM to the screen. No verification of the data is performed.
PAGE 101
Local Area Network Address ROM Test Figure 4–2 LAN Address ROM Format Address Octet 0 Address Octet 1 Address Octet 2 Address Octet 3 Address Octet 4 Address Octet 5 Checksum Octet 1 Checksum Octet 2 Checksum Octet 2 Checksum Octet 1 Address Octet 5 Address Octet 4 Address Octet 3 Address Octet 2 Address Octet 1 Address Octet 0 Address Octet 0 Address Octet 1 Address Octet 2 Address Octet 3 Address Octet 4 Address Octet 5 Checksum Octet 1 Checksum Octet 2 Test Pattern = FF Test Pattern = 00 Test Pattern =
PAGE 102
NCR 53C810 PCI-SCSI I/O Processor Tests NCR 53C810 PCI-SCSI I/O Processor Tests These tests check the NCR810 SCSI controller chip. The tests do not require a drive to be attached to the SCSI port and are meant to be a power-on check of the NCR810 chip’s low-level modes through programmed I/O issued from the CPU. There are no NCR810 scripts executing during these tests.
PAGE 103
NCR 53C810 PCI-SCSI I/O Processor Tests NCR810 Command/Status Register Test This test writes, reads, and compares all of the NCR810 command/status registers that are feasible to test. When the test finishes, it returns the registers to their initialized values. Console Command: ncr810_diag -t 3 Command Option: -lp: loop on write/read if the -lp option is specified.
PAGE 104
NCR 53C810 PCI-SCSI I/O Processor Tests NCR810 Interrupt Test This test verifies the interrupt connection between the NCR810 and the SIO controller to the CPU. A general purpose timer is enabled which generates an interrupt that is dispatched to the CPU through the SIO controller. The console PALcode dispatches to the NCR810_diag ISR, which clears the interrupt. Console Command: ncr810_diag -t 7 Miscellaneous Notes • These tests do not run in parallel with the SCSI exerciser tests.
PAGE 105
Watchdog Timer Interrupt Test Watchdog Timer Interrupt Test This test verifies the functionality of the watchdog timeout by its ability to handle a user programmed watchdog reset. This test checks the following logic: • Watchdog timer • Some reset logic • DS1386 TOY clock Watchdog Timer Interrupt Test The diagnostic-in-progress bit is set and a watchdog timeout is invoked by loading a short time value into the watchdog timeout register. The user is queried to be sure the watchdog LED is off.
PAGE 106
VME Interface Tests VME Interface Tests These tests verify the VME interface logic on the Digital Alpha VME 4 module, including the VME interface processor (VIP), the Cypress VIC064, the scatter/gather RAMs, and some of the interrupt paths from the VME corner to the Alpha processor. No VMEbus transactions are performed by these tests and therefore require no additional VMEbus modules. VIP PCI Configuration Register Test This test reads the first 8 longwords of VIP PCI configuration space.
PAGE 107
VME Interface Tests VME Scatter-Gather RAM Test This test verifies the integrity of the scatter/gather RAM by performing write, read, and verify of various patterns to the entire scatter/gather RAM. Console Command: vip_diag -t 4 Command Option: -dd: print detailed test information on each pass.
PAGE 108
4.4 Initialization Sequence The diagnostic test sequence for a full power-on reset and initialization is shown in Figures 4–3, 4–4, and 4–5.
PAGE 109
Figure 4–4 Console POST Flows B Notes LED Display A SCSI Test Console test B Heartbeat Test Console test C Interval Timer Tests Console test D Time-of-Year Tests Console test E Serial Com Port Tests Console test F Ethernet ROM Tests Console test G Ethernet Internal Loopback Tests Console test C ML013409 Diagnostics 4–31
PAGE 110
Figure 4–5 Console POST Flows C LED Display Notes H Watchdog Test Console test I VIP-VIC Tests Console test Console Prompt Console test ML013410 4–32 Diagnostics
PAGE 111
5 System Address Mapping This chapter describes the mapping of the 34-bit processor physical address space into memory and I/O space addresses. It also includes the translations of the processor-initiated address into a PCI address, and PCI-initiated addresses into physical memory addresses. 5.
PAGE 112
Figure 5–1 System Bus Address Map 2 0000 0000 Flash ROM Ethernet SCSI PMC Module VIP/VME Window VIP/VIC CSR VME S/G 2 000F FFFF Programmed by Firmware Programmed by Firmware Programmed by Firmware Programmed by Firmware 64 MB Programmed by Firmware 512 Byte Programmed by Firmware 128 KB Programmed by Firmware 384 MB Programmed VIP/VME by Firmware Window 512 MB Programmed PCI-System by Firmware Direct Mapped 2 GB Programmed Other Map I/O by Firmware 2 GB General Use 1 C000 0000 0 0000 0000 Cacheable Memo
PAGE 113
Table 5–1 System Bus Address Space Description sysAdr <33:32> sysAdr <31:28> 00 Address Space Description xxxx Cacheable memory space Accessed by the CPU instruction stream (Istream) or data stream (Dstream). Accessed by direct memory access (DMA). 01 0xxx Noncacheable memory space Accessed by the CPU (Istream or Dstream). Accessed by DMA. Can be used for a frame buffer on the DRAM bus. 01 100x 21071-CA CSRs The 21071-CA responds to all addresses in this space. Dstream access only.
PAGE 114
Table 5–1 (Cont.) System Bus Address Space Description sysAdr <33:32> sysAdr <31:28> 10 xxxx Address Space Description PCI sparse memory space 128 MB addressable PCI space. The lower address bits are used to determine byte masks and transaction length information. The 4 GB space is reduced to a 128 MB sparse space. Use this space when byte or word granularity is required. Read or write length is no more than a quadword. Reading other than the requested data is harmful.
PAGE 115
5.1.4 DECchip 21071-DA CSR Space (0x1A0000000 to 0x1AFFFFFFF) The DECchip 21071-DA responds to all accesses in this space. Section 7.4 specifies the registers and associated register addresses. Section 7.5 contains the register descriptions. 5.1.5 PCI Interrupt Acknowledge/Special Cycle Space (0x1B0000000 to 0x1BFFFFFFF) A read access to this space causes an interrupt acknowledge cycle on the PCI. Bits sysBus<6:3> are used to generate the byte enables on the PCI as specified in Table 5–2.
PAGE 116
Figure 5–2 shows the translation of system bus addresses to PCI bus I/O addresses. Table 5–2 shows how the byte enable bits and PCI ad<2:0> are generated from bits sysBus<6:3>.
PAGE 117
Table 5–2 PCI Sparse I/O Space Byte Enable Generation Length CPU Address <6:5> CPU Address <4:3> PCI Byte Enable1 PCI ad<2:0> Byte 00 00 1110 CPU address<7>, 00 01 00 1101 CPU address<7>, 01 10 00 1011 CPU address<7>, 10 11 00 0111 CPU address<7>, 11 00 01 1100 CPU address<7>, 00 01 01 1001 CPU address<7>, 01 10 01 0011 Word Tribyte Longword Longword CPU address<7>, 10 2 11 01 Illegal — 00 10 1000 CPU address<7>, 00 01 10 0001 CPU address<7>, 01 2 — 10 10
PAGE 118
5.1.7 PCI Configuration Space (0x1E0000000 to 0x1FFFFFFFF) A read or write access to this space causes a configuration read or write cycle on the PCI. There are two classes of targets: devices on the primary PCI bus and devices on the secondary PCI buses that are accessed through PCI-to-PCI bridge chips. During PCI configuration cycles, the meanings of the address fields vary depending on the intended target of the configuration cycle.
PAGE 119
Table 5–4 PCI Address Decoding for Primary Bus Configuration Accesses Device Number (sysAdr<20:16>) PCI ad<31:11> 00000 0000 0000 0000 0000 0000 1 00001 0000 0000 0000 0000 0001 0 00010 0000 0000 0000 0000 0010 0 00011 0000 0000 0000 0000 0100 0 00100 0000 0000 0000 0000 1000 0 00101 0000 0000 0000 0001 0000 0 00110 0000 0000 0000 0010 0000 0 00111 0000 0000 0000 0100 0000 0 01000 0000 0000 0000 1000 0000 0 01001 0000 0000 0001 0000 0000 0 01010 0000 0000 0010 0000 0000 0 01011 0000
PAGE 120
Peripherals that integrate multiple functional units (for example, SCSI, Ethernet, and so on) can provide configuration spaces for each function. Bits ad<10:8>, which are taken from bits sysAdr<15:13>, can be decoded by the peripheral to select one of eight functional units. Bits <31:11> are used to generate the IDSEL signals. Typically, the IDSEL# pin of each PCI peripheral is connected to a unique address line.
PAGE 121
5.1.8 PCI Sparse Memory Space (0x200000000 to 0x2FFFFFFFF) Access to PCI sparse memory space can have byte, word, tribyte, longword, or quadword granularity. The Alpha architecture does not provide byte, word, or tribyte granularity, which the PCI requires. To provide this granularity, the byte enable and byte length information is encoded in the lower address bits of this space (ad<7:3>).
PAGE 122
Figure 5–3 PCI Memory Space Address Translation 33 32 31 29 28 08 07 06 05 04 03 02 00 1 0 0 0 0 Length in Bytes HAXR0 31 Longword Address 27 26 Byte Offset 03 02 01 00 0 0 0 0 0 0 0 Address Translation for Lower 16M Bytes of PCI Memory Space 33 32 31 29 28 08 07 06 05 04 03 02 00 1 0 Non-Zero 31 HAXR1 27 26 Length in Bytes 00 Byte Offset Longword Address 31 27 26 03 02 01 00 0 0 Address Translation for Remaining 112M Bytes of PCI Memory Space LJ03938A.
PAGE 123
Table 5–5 PCI Sparse Memory Space Byte Enable Generation Length PCI Byte CPU CPU Address<6:5> Address<4:3> Enable1 PCI ad<2:0>2 Byte 00 00 1110 CPU address<7>, 00 01 00 1101 CPU address<7>, 00 10 00 1011 CPU address<7>, 00 11 00 0111 CPU address<7>, 00 00 01 1100 CPU address<7>, 00 01 01 1001 CPU address<7>, 00 10 01 0011 CPU address<7>, 00 11 01 Illegal3 — 00 10 1000 CPU address<7>, 00 01 10 0001 Word Tribyte Longword CPU address<7>, 00 3 — 10 10 Illegal 1
PAGE 124
One bit pair of cpucwmask<1:0>, <3:2>, <5:4>, and <7:6> must have a value of 01 (binary). The other fields must be 00. The location of the 01 field indicates whether the data reference is byte, word, tribyte, or longword (respectively). Similarly, if a quadword is written to the PCI, software must execute an STQ instruction to the corresponding address. The only legal value on cpucwmask<7:6> in sparse space is 11000000.
PAGE 125
• On write transactions, ad<4:2> is generated from cpucwmask<7:0>. If the lower longword is to be written, ad<2> is 0; if the lower longword is masked out and the upper longword is to be written, ad<2> is 1. The number of longwords written on the PCI is directly obtained from cpucwmask<7:0>. Any combination of cpucwmask<7:0> is allowed by the 21072 chipset.
PAGE 126
Table 5–6 PCI Target Window Enables PCI_MASK<31:20>1 Window Size Value of n2 0000 0000 0000 1 MB 20 0000 0000 0001 2 MB 21 0000 0000 0011 4 MB 22 0000 0000 0111 8 MB 23 0000 0000 1111 16 MB 24 0000 0001 1111 32 MB 25 0000 0011 1111 64 MB 26 0000 0111 1111 128 MB 27 0000 1111 1111 256 MB 28 0001 1111 1111 512 MB 29 0011 1111 1111 1 GB 30 0111 1111 1111 2 GB 31 1111 1111 1111 1 3 4 GB 32 Combinations of bits not shown in PCI_MASK<31:20> are not supported.
PAGE 127
Figure 5–4 PCI Target Window Compare Scheme n n -1 31 PCI Address 20 19 13 12 Peripheral Page Number Compare n n -1 31 PCI Base Register Offset Hit 20 XXX n n -1 31 PCI Mask Register 00 0000000 20 111 (Determines n ) LJ-03955.AI When an address match occurs with a PCI target window, the 21071-DA translates the 32-bit PCI address ad<31:0> to a 34-bit processor byte address (actually a 29-bit hexword address).
PAGE 128
Table 5–7 PCI Target Address Translation—Direct Mapped PCI_MASK<31:20> Translated Base <32:5> 0000 0000 0000 T_BASE<32:20>:PCI ad<19:5> 0000 0000 0001 T_BASE<32:21>:PCI ad<20:5> 0000 0000 0011 T_BASE<32:22>:PCI ad<21:5> 0000 0000 0111 T_BASE<32:23>:PCI ad<22:5> 0000 0000 1111 T_BASE<32:24>:PCI ad<23:5> 0000 0001 1111 T_BASE<32:25>:PCI ad<24:5> 0000 0011 1111 T_BASE<32:26>:PCI ad<25:5> 0000 0111 1111 T_BASE<32:27>:PCI ad<26:5> 0000 1111 1111 T_BASE<32:28>:PCI ad<27:5> 0001 1111 1111 T_BA
PAGE 129
Figure 5–5 Scatter-Gather Map Page Table Entry in Memory 63 32 MBZ 31 21 20 MBZ 01 Page Address <32:13> 00 Valid LJ03956A.AI The size of the scatter-gather map table is determined by the size of the PCI target window as defined by the PCI mask register (see Table 5–8). Because the scatter-gather map is located in system memory, bit sysBus<33> is always zero. Bits sysBus<32:2> are obtained from the translated base register and the PCI address.
PAGE 130
Table 5–8 Scatter-Gather Map Address PCI_MASK<31:20> Scatter-Gather Map Table Size Scatter-Gather Map Address<32:3> 0000 0000 0000 1 KB T_BASE<32:10>:PCI ad<19:13> 0000 0000 0001 2 KB T_BASE<32:11>:PCI ad<20:13> 0000 0000 0011 4 KB T_BASE<32:12>:PCI ad<21:13> 0000 0000 0111 8 KB T_BASE<32:13>:PCI ad<22:13> 0000 0000 1111 16 KB T_BASE<32:14>:PCI ad<23:13> 0000 0001 1111 32 KB T_BASE<32:15>:PCI ad<24:13> 0000 0011 1111 6 KB T_BASE<32:16>:PCI ad<25:13> 0000 0111 1111 128 KB T_BASE<32
PAGE 131
Figure 5–6 Scatter-Gather Map Translation of PCI Bus Address to System Bus Address n 31 PCI Address 13 12 Peripheral Page Number 05 04 00 Offset Compare sysBus Base Address (Translated Base Register) Scatter-Gather Map Address Driven on sysBus n -10 n -11 33 07 T_Base 0000 n -10 n -11 33 20 03 01 Scatter-Gather Entry Scatter-Gather Map in Main Memory Physical Memory Location Driven on sysBus 33 32 13 12 sysBus Page Number 05 Offset LJ03957A.AI 6.
PAGE 132
PAGE 133
6 Cache and Memory Subsystem The cache and memory subsystem serves as the memory controller and the system bus (sysBus) controller. Figure 6–1 Cache and Memory Subsystem CPU Bcache Cache and Memory Controller System Bus (sysBus) Data Path 4 chips Main Memory ML013274 The components of the cache and memory subsystem are distributed between the DECchip 21071-CA and the DECchip 21071-BA. Together, the chips are the interface between the system bus, main memory, and the Bcache (see Figure 6–2).
PAGE 134
Figure 6–2 Address and Data Paths of Cache and Memory Tag Adr Ctrl L2 Cache Ctrl SysAdr CPU Cache 21071-CA Memory Address and Control sysData <15:0> Memory DRAMs sysData <127:0> Check <21:0> 32 Bits 21071-BA0 32 Bits 32 Bits 21071-BA1 32 Bits 21071-BA2 32 Bits 32 Bits 32 Bits 21071-BA3 32 Bits memData <127:0> memECC <21:0> 21071-DA Data Path Bit Assignments sysData Lines memData Lines 21071-BA0 <31:0> 21071-BA1 <63:32> 21071-BA2 <95:64> 21071-BA3 <127:96> memData <31:0> memData <63:32> memData
PAGE 135
Figure 6–3 21071-CA Block Diagram tagadr<31:17> adr<33:5> Write Address Tag Compare Address Read Address Generation Write Buffer Address Row Row and Column Generation Col b0<3:0>_adr<11:0> 48 b<3:0>_ras<1:0>_l SysBus Control L2 Cache Control Dath Path Control SysBus and L2 Cache Control Write Bank Memory Bank Generation Read Bank 8 b<3:0>_ras<1:0>b_l Memory Control 8 b<1:0>_cas<3:0>b_l 8 b0<3:0>_we_l 4 b<3:0>_we_l 4 ML013275 The following list summarizes the functions of the DECchip 21071-CA:
PAGE 136
6.1 System Bus Interface The CPU, DECchip 21071-CA, PCI host bridge, cache, and memory communicate with each other through the system bus. The system bus is the processor pin bus with additional signals for DMA transaction control, arbitration, and cache control. 6.1.1 Arbitration on the System Bus The DECchip 21071-CA arbitrates between the CPU and 21071-DA chip when these components request use of the system bus or the Bcache.
PAGE 137
6.2 Bcache Control Figure 6–4 shows the implementation of a cache subsystem with a 2 MB cache. Figure 6–4 Cache Subsystem for a 2 MB Cache Bcache SIMMs (2 MB) AlphaPC64.
PAGE 138
6.3.1 Memory Organization A bank of memory is one width of DRAMs, 128 bits, implemented with DIMMs. The DECchip 21071-CA supports one or two banks of DRAM where each bank consists of two DIMMs of the same size and speed. The 21071-CA supports 16 MB to 128 MB of main memory. The chip controls two banks of DRAM DIMMs. Each bank contains two 80-bit DIMMs to support the 128-bit data path and longword error checking/correction (ECC). The DIMM sizes are 1 MB x 80 (8 MB), 2 MB x 80 (16 MB), and 4 MB x 80 (32 MB).
PAGE 139
6.3.2 Memory Address Generation Each bank has a programmable base address and size. The incoming physical address is compared with the memory ranges of all banks. The number of bits that are compared depends on the size of the bank. The programmable base address of a bank set must be aligned to the natural size boundary. For example, an 8 MB bank set must start on an 8 MB boundary. 6.3.
PAGE 140
6.3.7 Presence Detect Logic The DECchip 21071-CA supports loading the status of 32 presence detect bits from the memory configuration registers 0 to 3 and the memory identification register after reset. 6.
PAGE 141
Table 6–1 identifies all banks; only Bank 0 and 1 are used.
PAGE 142
Table 6–1 (Cont.
PAGE 143
6.6 Description of CSRs 6.6.1 General Control Register The general control register contains status information that affects the memory, cache, and system bus controllers. The register is shown in Figure 6–6 and is defined in Table 6–2. Figure 6–6 General Control Register: 0x180000000 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 MBZ MBZ BC_BADAP BC_FRCP BC_FRCV BC_FRCD BC_FRCTAG BC_IGNTAG BC_LONGWR BC_NOALLOC BC_EN WIDEMEM MBZ SYSARB MBZ LJ-04178.
PAGE 144
Table 6–2 General Control Register Field Name Type <15:14> Reserved MBZ Description — 1 <13> BC_BADAP RW, 0 Bcache force bad address parity. When set, the tag address parity is loaded as an invalid address, independent of the value of the BC_ FRCTAG bit. <12> BC_FRCP RW, 0 Bcache force parity. Sets the parity bit on the next cache fill. <11> BC_FRCV RW, 0 Bcache force valid. Sets the valid bit on the next cache fill. <10> BC_FRCD RW, 0 Bcache force dirty.
PAGE 145
Table 6–2 (Cont.) General Control Register Field Name Type Description <5> BC_EN RW, 0 Bcache enable. When clear, the L2 cache is disabled and the cache state machine does not probe the cache. <4> WIDEMEM RO Wide memory size. Reads the status of the widemem input pin. Returns 1 for the 128-bit memory interface. <3> Reserved MBZ — <2:1> SYSARB RW, 0 DMA arbitration mode. Determines arbitration scheme for system bus transactions.
PAGE 146
Figure 6–7 Error and Diagnostic Status Register: 0x180000020 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 WRPEND LDXLLOCK PASS 2 MBZ CREQCAUSE VICCAUSE DMACAUSE NXMERR BC_TCPERR BC_TAPERR LOSTERR LJ-04179.AI Table 6–3 Error and Diagnostic Status Register Field Name Type Description <15> WRPEND RO, O Write pending. When set, indicates that valid write data is stored in the write buffer. <14> LDXLLOCK — LDx_L locked.
PAGE 147
Table 6–3 (Cont.) Error and Diagnostic Status Register Field Name Type Description <8:6> CREQCAUSE RO Cycle request caused error. Indicates the DMA or CPU cycle request type that caused the error. Contains a copy of either the cpucreq or iocmd signal lines, depending on DMACAUSE<4>. Locked with the error address. Only valid when an error is indicated on BC_TAPERR, BC_TCPERR, or MEMERR. <5> VICCAUSE RO Victim write caused error.
PAGE 148
6.6.3 Tag Enable Register The tag enable register (TAGEN), shown in Figure 6–8, indicates which bits of the cache tag are compared to sysadr<33:5>: • If a bit is 1, the bits in sysadr<33:5> and systag<31:17> are compared. Bits <15:1> in the register represent systag<31:17>. • If a bit is 0, no comparison is made, and the systag bit is assumed to be tied low on the module through a resistor. This register is not initialized.
PAGE 149
Table 6–4 Cache Size Tag Enable Values TAGEN<15:0> Compared Bits 0000 0000 0000 00001 None 4 GB 1000 0000 0000 0000 <31> 2 GB 1100 0000 0000 0000 <31:30> 1 GB 1110 0000 0000 0000 <31:29> 512 MB 1111 0000 0000 0000 <31:28> 256 MB 1111 1000 0000 0000 <31:27> 128 MB 1111 1100 0000 0000 <31:26> 64 MB 1111 1110 0000 0000 <31:25> 32 MB 1111 1111 0000 0000 <31:24> 16 MB 1111 1111 1000 0000 <31:23> 8 MB 1111 1111 1100 0000 <31:22> 4 MB 1111 1111 1110 0000 <31:21> 2 MB 1111 1111
PAGE 150
Table 6–5 Maximum Memory Tag Enable Values TAGEN<15:0> Compared Bits 1111 1111 1111 11101 <31:17> Memory Size 4 GB 0111 1111 1111 1110 <30:17> 2 GB 0011 1111 1111 1110 <29:17> 1 GB 0001 1111 1111 1110 <28:17> 512 MB 0000 1111 1111 1110 <27:17> 256 MB 0000 0111 1111 1110 <26:17> 128 MB 0000 0011 1111 1110 <25:17> 64 MB 0000 0001 1111 1110 <24:17> 32 MB 0000 0000 1111 1110 <23:17> 16 MB 0000 0000 0111 1110 <22:17> 8 MB 0000 0000 0011 1110 <21:17> 4 MB 0000 0000 0000 1110 <1
PAGE 151
Figure 6–9 Error Low Address Register: 0x180000080 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ERR_LADR<20:5> LJ-04181.AI 6.6.5 Error High Address Register When an error sets the BC_TAPERR, BC_TCPERR, or NXMERR bit in the error and diagnostic status register, the error high address register latches the highorder bits of the sysadr<33:21> address that caused the error. If a victim read caused the error, the victim address is not latched. Instead, the address of the transaction is latched.
PAGE 152
Figure 6–11 LDx_L Low Address Register: 0x1800000C0 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 LDXL_LARD<20:5> LJ-04183.AI 6.6.7 LDx_L High Address Register The LDx_L high address register stores the high-order bits of the latched address. The register is shown in Figure 6–12. Bits <12:0> represent sysadr<33:21>. This register is read-only and is not initialized. Figure 6–12 LDx_L High Address Register: 0x1800000E0 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 MBZ LDXL_HARD<33:21> LJ-04184.AI 6.
PAGE 153
Figure 6–13 Presence Detect Low-Data Register: 0x180000280 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PRES_DET<15:0> LJ-04186.AI 6.6.8.2 Presence Detect High-Data Register After a reset operation, presence detect data are shifted from the memory configuration and memory ID. The presence detect high-data register stores the high-order bits of the presence detect data. Bits <15:0> in the register represent the shifted data bits <31:16>. The register is shown in Figure 6–14.
PAGE 154
Figure 6–15 Bank 0 Base Address Register: 0x180000800 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 S0_BASEADR<33:23> MBZ LJ-04188.AI The base address of each bank must begin on a naturally aligned boundary. For example, for a bank with 2n addresses, the n least significant bits must be zero. Register bits <4:0> are reserved and must be zero. 6.6.8.4 Configuration Registers Each memory bank set has a configuration register that contains mode bits, memory address generation bits, and bank decoding bits.
PAGE 155
Table 6–6 Configuration Register for Banks 0 and 1 Field Name1 Type Description <15:9> Reserved MBZ — <8:6> RW Column address selection. Indicates the number of valid column bits expected at the DRAMs. Used with memory width information to generate row or column addresses. Memory interface width is set at 128 bits.
PAGE 156
Table 6–6 (Cont.) Configuration Register for Banks 0 and 1 Field Name1 Type Description <4:1> S0_SIZE RW Bank size in Mbytes. Indicates the size of the bank and any subbanks. The size defines which bits are used in comparing the base address with the physical address (PA) and for generating the subset. S0_SIZE<3> must be set to 0.
PAGE 157
The description of the parameters also indicates the corresponding DRAM parameter. Bank 0’s timing register A is shown in Figure 6–17 and is defined in Table 6–7. Figure 6–17 Bank Set 0 Timing Register A: 0x180000C00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 MBZ S0_RDLYCOL S0_RDLYROW S0_COLHOLD S0_COLSETUP S0_ROWHOLD S0_ROWSETUP ML013278 Table 6–7 Timing Register A Field Name Type Description <15> Reserved MBZ — <14:12> S0_RDLYCOL RW, 1 Read delay from column address.
PAGE 158
Table 6–7 (Cont.) Timing Register A Field Name Type Description <6:4> S0_COLSETUP RW, 0 Column address setup (tASC ) to first CAS assertion and write enable setup (tCWL ) to CAS assertion. Used to determine first b0_cas<1:0>_l assertion after column address and b<1:0>_cas<1:0>_l assertion after b0_l<3:0>_we_l. The maximum of the two setup values must be programmed. A programmed value of 7 is illegal. P rogrammed value = desired value 0 1. <3:2> S0_ROWHOLD — Row address hold.
PAGE 159
Table 6–8 Timing Register B Field Name Type Description <15:14> Reserved MBZ — <13:11> S0_WHOLD0COL RW, 1 Write hold time from column address. Used only for the first data when starting in page mode. Write data is valid with the column address and is held valid for S8_WHOLD0COL + 2 cycles after the column address. P rogrammed value = desired value 0 2. <10:8> S0_WHOLD0ROW RW, 1 Write hold time from row address. Hold time of first write data from first row address.
PAGE 160
Figure 6–19 Global Timing Register: 0x180000200 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 MBZ GTR_MAX_RAS_WIDTH GTR_RP LJ-04193.AI Table 6–9 Global Timing Register Field Name Type Description <15:6> Reserved MBZ — <5:3> GTR_MAX_RAS_WIDTH — Maximum RAS assertion width as a multiple of 128 memory clock cycles. When this count is reached, the signal b<3:0>_ras0_l is deasserted at the end of the ongoing transaction.
PAGE 161
The refresh timing register is shown in Figure 6–20 and is defined in Table 6–10. Figure 6–20 Refresh Timing Register: 0x180000220 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 FORCE_REF MBZ REF_INTERVAL REF_RASWIDTH REF_CAS2RAS DISREF LJ-04194.AI Table 6–10 Refresh Timing Register Field Name Type Description <15> FORCE_REF RW, 1 Force refresh. Reads as 0. Writing a 1 to this bit causes a single memory refresh. Resets the internal refresh interval counter.
PAGE 162
Table 6–10 (Cont.) Refresh Timing Register Field Name Type Description <0> DISREF RW, 0 Disable refresh. Refresh operations are not performed when DISREF is set. The other timings in this register must not change while this bit is set. FORCE_REF overrides DISREF. 6.7 Data Path The data path consists of the buffers and their communications buses. This section gives a functional overview of the 21071-BA chips that make up the data bus configuration.
PAGE 163
6.7.1 Memory Read Buffer The memory read buffer stores data from memory before the data is sent to the CPU or returned to DMA in the DMA read buffer. Each chip stores 4 longwords of data and the corresponding ECC bits in the memory read buffer. 6.7.2 I/O Read Buffer and Merge Buffer On CPU-initiated memory transactions, the buffer acts as the merge buffer. On CPU-initiated I/O read transactions addressed to or through the PCI host bridge (the 21071-DA chip), the buffer acts as the I/O read buffer.
PAGE 164
6.7.5 Memory Write Buffer The memory write buffer has four entries for each chip. Each entry has four longwords and corresponding ECC bits. The system bus interface loads the buffer and the memory controller unloads it (both are 21071-CA functions). 6.7.6 Error Handling The data path chips perform ECC on DMA transactions. The data is checked for ECC errors during a DMA read transaction or a DMA-masked write transaction.
PAGE 165
7 PCI Host Bridge The 21071-DA chip is the bridge between the PCI local bus and the system bus, as shown in Figure 7–1. Figure 7–1 PCI Host Bridge EpiData bus 32 Bits PCI Host Bridge (21071-DA) PCI BUS 32 Bits ML013280 As a PCI host bridge, the 21071-DA chip contains all control functions of the bridge and some data path functions. Figure 7–2 shows a block diagram of the 21071-DA chip.
PAGE 166
Figure 7–2 DECchip 21071-DA Block Diagram adr<33:5> Address MUX and Merge Logic DMA Write I/O Read Data DMA Read I/O Write Data I/O Address 8-Entry TLB PCI cbe<3:0> PCI Window Hit Detection Parity Check Generation PCI par epiErr<31:0> CSRs and Error Logging DMA Read Address Read Bypass MUX DMA Write Address 4-Entry DMA Write Address FIFO PCI ad<31:0> 3 LW DMA Read I/O Write Buffer epiData<31:0> ML013460 The PCI host bridge serves as the interface between the PCI local bus and the 21064A microproce
PAGE 167
7.1.2 Buffering System Bus Transactions Write-and-run I/O write transactions use a 1-entry write buffer. One I/O read transaction is initiated by the CPU. The I/O read buffer is a temporary buffer and is invalidated at the end of each I/O read transaction. To function correctly, the CPU must be configured in wrap mode. The PCI host bridge supports wrapped mode only on transactions initiated by the CPU. The requested quadword is the only one that is returned on I/O read transactions. 7.1.
PAGE 168
7.2.3 Burst Length and Prefetching for PCI bus On write transactions directed toward main memory, the PCI host bridge supports a maximum burst length of 16 longwords. For the maximum burst, the write transaction must start on an even cache-line boundary with PCI ad<5> = 0 and PCI ad<4:2> = 0. The transaction is terminated using a PCI disconnect after the sixteenth longword has been received. In all other cases, the burst is less than 16 longwords.
PAGE 169
7.3.3 Data Coherency The two agents that must synchronize their data transfers are the CPU and any PCI device. The PCI host bridge maintains data coherency and synchronization between the agents using the following mechanisms: • Maintains strict ordering of DMA write transactions initiated on the PCI bus. • Allows DMA read transactions to bypass write transactions that are not to the same address (double cache line) but maintains strict ordering between read and write transactions to the same address.
PAGE 170
7.3.4 Interrupts When the PCI host bridge has errors to report, it uses the int_hw0 signal to interrupt the CPU. It does not distinguish between hard and soft errors when asserting the interrupt signal. The PCI host bridge does not provide an interval timer interrupt so this functionality must be provided to the CPU by some other device in the system. In addition, interrupts from other PCI devices or from a PCI interrupt controller must be sent directly to the CPU without intervention.
PAGE 171
7.3.7 Retry Timeout The PCI host bridge implements a timeout mechanism to terminate CPU-initiated transactions that do not complete on the PCI bus because of too many disconnects or retries. When it initiates a CPU transaction on the PCI bus, the PCI host bridge counts the number of times it is retried or disconnected. If the number exceeds 224 , it flags an error to the CPU and aborts the transaction. 7.3.
PAGE 172
Table 7–1 (Cont.
PAGE 173
Table 7–1 (Cont.) DECchip 21071-DA CSR Addresses Address16 Register Name 1 A000 03E0 TLB 7 data register 1 A000 0400 Translation buffer invalidate all register (TBIA) 7.5 Description of CSRs The CSRs are 16 bits wide and are addressed on cache-line boundaries. Write transactions to read-only registers could result in UNPREDICTABLE behavior; read transactions are nondestructive. Only bits <15:0> of each register are defined. Only zeros should be written to unspecified bits within a CSR.
PAGE 174
Figure 7–3 Diagnostic Control/Status Register: 0x1A0000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PASS2 MBZ PCMD D_BYP<1:0> MERR IPTL UMRD CMRD NDEV TABT IOPE DDPE MBZ LOST IORT DPEC DCEI PENB MBZ TENB LJ-04195.AI Table 7–2 Diagnostic Control/Status Register Field Name Type Description <31> PASS2 RO Pass 2. Chip version reads low on pass 1 and high on pass 2. <30:22> Reserved MBZ — <21:18> PCMD RO PCI command.
PAGE 175
Table 7–2 (Cont.) Diagnostic Control/Status Register Field Name Type Description <17:16> D_ BYP<1:0> RW, 0 Disable read bypass. Controls the order of PCIinitiated memory read transactions with respect to PCI-initiated memory write transactions. The three modes are shown in the following table.
PAGE 176
Table 7–2 (Cont.) Diagnostic Control/Status Register Field Name Type Description <14> IPTL RWC, 0 Invalidate page table lookup. This bit is set when the longword scatter-gather map entry being accessed is invalid. Bits ad<31:0> are logged in the PCI error address register, if it is not already locked. <13> UMRD RWC, 0 Uncorrectable memory read data.
PAGE 177
Table 7–2 (Cont.) Diagnostic Control/Status Register Field Name Type Description <6> LOST RWC, 0 Lost error. This bit is set by a 21071-DA error condition when the address register for that error is locked because of a previous error. In this case, error information for the second error is lost. The logged address information in the system bus Error Address register or the PCI error address register remains valid for the initial error condition. <5> IORT RWC, 0 I/O retry timeout.
PAGE 178
Figure 7–4 PCI Error Address Register: 0x1A0000020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PCI_ERR<31:0> LJ-04197.AI Table 7–3 PCI Error Address Register Field Name Type Description <31:0> PCI_ERR<31:0> RO PCI error. Stores the address sent out on the PCI bus ad<1:0> as a result of an I/O transaction. The field logs the address of the errors indicated by the NDEV, TABT, IOPE, DDPE, IPTL, and IORT bits in the DCSR.
PAGE 179
Table 7–4 System Bus Error Address Register Field Name Type Description <31:3> SYS_ERR<33:5> RO System bus error address. Stores the address sent on system bus sysadr<33:5> as a result of a DMA transaction. The field logs errors indicated by the MERR, UMRD, or CMRD bits in the DCSR, and is valid only when one of these bits is set. If an error bit is set, a subsequent error of the same type does not update the address logged in this register and the LOST bit is set in the DCSR.
PAGE 180
Table 7–5 Translated Base Registers 1 and 2 Field Name Type Description <31:9> T_BASE<32:10> RW Translated base. If scatter-gather mapping is disabled, T_BASE specifies the base CPU address of the translated PCI address for the PCI target window. If scatter-gather mapping is enabled, T_BASE specifies the base CPU address for the scatter-gather map table for the PCI target window. <8:0> Reserved MBZ — 7.5.
PAGE 181
Table 7–6 (Cont.) PCI Base Registers 1 and 2 Field Name Type Description <19> WENB RW, 0 Window enable. When clear, the PCI target window is disabled and does not respond to PCI-initiated transfers. When set, the PCI target window is enabled and responds to PCI-initiated transfers that hit in the address range of the target window. This bit must be disabled by the processor when modifying any of the PCI target window registers (base, mask, or translated base).
PAGE 182
Table 7–7 PCI Mask Registers 1 and 2 Field Name Type Description <31:20> PCI_MASK<31:20> RW PCI mask. This field specifies the size of the PCI target window; it is also used in the PCI-to-CPU address translation. <19:0> Reserved MBZ — 7.5.8 Host Address Extension Register 0 The host address extension register is hardcoded to zero. A read transaction from this register returns zero; a write transaction has no effect. The register is shown in Figure 7–9.
PAGE 183
Table 7–8 Host Address Extension Register 1 Field Name Type Description <31:27> EADDR<4:0> RW, 0 Extension address. This field is used as the five high-order PCI address bits (ad<31:27>) for CPU-initiated transactions to PCI memory. <26:0> Reserved MBZ — 7.5.10 Host Address Extension Register 2 The host address extension register 2 generates ad<31:24> on CPU-initiated transactions addressing PCI I/O space. It also generates ad<1:0> during PCI configuration read and write transactions.
PAGE 184
7.5.11 PCI Master Latency Timer Register The PCI master latency timer register defines the latency timer period. Define a nonzero value during system configuration. The register is shown in Figure 7–12 and is defined in Table 7–10. Figure 7–12 PCI Master Latency Timer Register: 0x1A00001E0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 MBZ PMLC<7:0> LJ-04204.
PAGE 185
Figure 7–13 TLB Tag Registers 0 Through 7: 0x1A0000200 to 0x1A00002E0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PCI_PAGE<31:13> EVAL MBZ LJ-04205.AI Table 7–11 TLB Tag Registers 0 Through 7 Field Name Type Description <31:13> PCI_PAGE<31:13> RO PCI page. Specifies the PCI page address (tag) for the translated CPU page address in the associated TLB data register. <12> EVAL RO Entry valid.
PAGE 186
Table 7–12 TLB Data Registers 0 Through 7 Field Name Type Description <31:21> Reserved MBZ — <20:1> CPU_PAGE<32:13> RO CPU page. Bits <32:13> of the translated CPU address can be read or written through this field. <0> Reserved — MBZ 7.5.14 Translation Buffer Invalidate All Register: 0x1A0000400 The translation buffer invalidate all register (TBIA) is write-only. A write transaction to this register invalidates all valid entries in the scatter-gather map TLB.
PAGE 187
8 PCI bus The PCI bus is the base for the I/O subsystem. All I/O components are connected by the 32-bit, 5 V only, PCI implementation and are called PCI devices. Figure 8–1 shows a block diagram of the I/O subsystem.
PAGE 188
Figure 8–1 PCI Bus and Interfaces to the I/O Subsystem To the sysBus (CPU, Memory, Bcache) PCI Host Bridge (21071-DA) PCI to Nbus Bridge Nbus PCI Bus 32 Bits PCI-VME Bridge SCSI Controller PCI to PCI Bridge 21052 Ethernet Controller PMC Adapter Module Option: PCI (PMC) Module 1 Option: PCI (PMC) Module 2 VME Connectors ML013281 The base address of each PCI device, except the Nbus interface (SIO), is configured by the Digital Alpha VME 4 firmware.
PAGE 189
8.1 Ethernet Controller The physical connection to the network is the Ethernet twisted-pair connector located on the front panel of the module. The Ethernet controller is based on the DECchip 21040-AA. This chip is a PCIbased Ethernet solution that keeps processor intervention in LAN control to a minimum.
PAGE 190
Figure 8–2 PCI Configuration Registers Device ID = 0002h Vendor ID = 1011h : 00001000 Status Command : 00001004 Class Code N/S Don't Care Rev ID : 00001008 N/S : 0000100C Latency Timer I/O Base Address (CBIO) : 00001010 Memory Base Address (CBMA) : 00001014 Reserved : 00001018 Reserved : 00001028 Reserved : 0000102C N/S (=Not Supported) : 00001030 Reserved : 00001034 Reserved : 00001038 X X Int Pin Int Line Driver Area (CFDA) : 0000103C : 00001040 Reserved Reserved : 000
PAGE 191
Table 8–1 Ethernet Controller CSRs Register Meaning Address CSR0 Bus mode register xxxx xx00H CSR1 Transmit poll demand xxxx xx08H CSR2 Receive poll demand xxxx xx10H CSR3 Rx list base address xxxx xx18H CSR4 Tx list base address xxxx xx20H CSR5 Status register xxxx xx28H CSR6 Serial command register xxxx xx30H CSR7 Interrupt mask register xxxx xx38H CSR8 Missed frame register xxxx xx40H CSR9 ENET ROM register xxxx xx48H CSR10 Reserved xxxx xx50H CSR11 Full-duplex regist
PAGE 192
8.1.4 Ethernet Address The Ethernet ID address for the Digital Alpha VME 4 assembly is stored in an on-board SROM, a 20-pin socketed PLCC. The Ethernet controller’s ENET ROM register (CSR9) can read the SROM. Each read access initiates 8-bit serial read cycles from the ENET ROM. Writing to the register resets the pointer of the ENET ROM to its first location. Figure 8–3 shows the ENET ROM register.
PAGE 193
8.2.2 SCSI ID The default SCSI ID is 7. You set the SCSI ID by writing the SCSI controller’s SCID register (offset 0x04). To do this, use the following console command: >>> set PKA0_HOST_ID n For example, if you enter set PKA0_HOST_ID 4, the embedded SCSI controller assumes a SCSI ID of 4. 8.2.3 Programming The SCSI controller can affect high-level SCSI operations with very little intervention from the processor.
PAGE 194
Figure 8–4 PCI Configuration Block Device ID = 0001h Vendor ID = 1000h : 00002000 Status Command : 00002004 Class Code N/S Don't Care Latency Timer Rev ID : 00002008 N/S : 0000200C I/O Base Address (SCSI_IO_BASE) : 00002010 Memory Base Address (SCSI_MEM_BASE) : 00002014 Reserved : 00002028 Reserved : 0000202C N/S (=Not Supported) : 00002030 Reserved : 00002034 Reserved : 00002038 X X X X Operating registers mapped to bytes 80h to FFh.
PAGE 195
Table 8–2 SCSI Controller CSRs Label R/W Description Offset SCNTL0 R/W SCSI Control 0 00 SCNTL1 R/W SCSI Control 1 01 SCNTL2 R/W SCSI Control 2 02 SCNTL3 R/W SCSI Control 3 03 SCID R/W SCSI Chip ID 04 SXFER R/W SCSI Transfer 05 SDID R/W SCSI Destination ID 06 GPREG R/W General Purpose 07 SFBR R/W 1st Byte Rx’ed 08 SOCL R/W Output Cntrl Latch 09 SSID R Selector ID 0A SBCL R/W Bus Control Lines 0B DSTST R DMA Status 0C SSTAT0 R SCSI Status 0 0D SSTAT
PAGE 196
Table 8–2 (Cont.
PAGE 197
8.3 PCI I/O Companion Card You can connect an optional PMC I/O companion card to the I/O module. This card contains a 21052 PCI-to-PCI bridge chip and two sets of PCI mezzanine card (PMC) connectors that allow you to add one double-width or two single-width PCI PMC modules. One of the PMC connector sets includes a third connector that allows I/O access through the P2 connector. PCI bus arbitration supports two PCI devices with up to four interrupt request lines each.
PAGE 198
PAGE 199
9 Nbus The Nbus is a special case of an ISA bus. The Nbus is a simple 8-bit data, 16-bit address, nonmultiplexed resource bus that interfaces with the PCI bus through the Super I/O (SIO) chip (Intel 82378IB). The interface translates PCI I/O references to the Nbus into simple read and write cycles to the resources hanging off the Nbus lines, as shown in Figure 9–1.
PAGE 200
• NVRAM • Interval timers The bottom 1 MB in PCI sparse memory space is mapped onto the Nbus for use by the flash ROM. These address regions are negatively decoded and are not affected by any other PCI device that is programmed to positively decode PCI addresses. The CPU can access the Nbus devices in I/O space on a byte-by-byte basis. Digital Alpha VME 4 only supports single-byte accesses to all Nbus locations. Most resources of the Nbus are accessed as the least-significant byte of aligned longwords.
PAGE 201
Figure 9–2 SIO Configuration Block Device ID = 0484h Vendor ID = 8086h : 00004000 Status Command : 00004004 Class Code Rev ID : 00004008 : 0000400C to 0000403F Reserved PCI Control : 00004040 MEMCS# Control (not used) : 00004044 ISA Addr Decode (not used) : 00004048 ISA Bus Control : 0000404C Reserved : 00004050 MEMCS# Attributes (not used) : 00004054 : 00004058 to 000040FF Reserved ML013285 9.1.1.
PAGE 202
9.1.1.2 ISA Controller Recovery Timer Register The ISA controller recovery timer register (offset +4Ch) is one of two bytewide registers used as the Nbus control word. The I/O recovery mechanism in the SIO chip is used to add recovery delay between the I/O cycles originating in the PCI bus and directed to the Nbus. Since only 8-bit cycles are supported, only bits <6:3> of the register are significant. Bits <6:3> define the number of system-clock ticks inserted between back-to-back cycles.
PAGE 203
Register CPU Address Nbus Offset Module display control 1 C001 0000 800 Module configuration 1 C001 0020 801 Interrupt register 1 1 C001 0040 802 Interrupt register 2 1 C001 0060 803 Interrupt register 3 1 C001 0080 804 Interrupt register 4 1 C001 00A0 805 Memory configuration 0 1 C001 00C0 806 Memory configuration 1 1 C001 00E0 807 Memory configuration 2 1 C001 0100 808 Memory configuration 3 1 C001 0120 809 Reset reason 1 1 C001 0140 80A Memory identification 1 C001 01
PAGE 204
Figure 9–3 Module Display Control Register 31 08 07 06 05 04 03 02 01 00 MOD_DISP_REG : Don't Care Brightness Control Display Character ML013287 The display character is stored in bits <6:0>. The most significant bit (bit <7>) can be set to increase the brightness of the display. Figure 9–4 shows the character set of the display. The numbers along the lefthand edge are the most-significant hexadecimal digit of the character number, while the least-significant is along the top.
PAGE 205
This read-only register contains information relating to module revision, CPU speed, and SCSI options. The information read from this register is hardwired on the module and is unaffected by resets. A write of 1 to bit 0 of this register clears the Periodic Real-Time timer. Figure 9–5 shows the module configuration register.
PAGE 206
Table 9–2 (Cont.) Module Configuration Register Field Name Type Description <6:5> CPU ID RO Determine the speed of the CPU according to the following table: <6:5> Definition 00 224 MHz 01 288 MHz 10 Reserved 11 Reserved 9.2.3 Interrupt and Interrupt Mask Registers 1, 2, 3, 4 See Chapter 11 for descriptions of these registers. 9.2.
PAGE 207
These registers are read-only. The values are loaded from memory DIMMs, identified in Table 2–8 at power-up. A complete description of the memory DIMMs is in Chapter 6. Table 9–3 DIMM Identification DIMM J# DRAM# Bank# Memory Configuration Register 2 0 0 0 3 1 0 1 4 1 1 3 5 0 1 2 DRAM0 refers to the DIMM array containing memory data lines 0 - 63. DRAM1 refers to the DIMM array containing memory data lines 64 - 127.
PAGE 208
Figure 9–7 Memory Identification Register 31 MEM_ID_REG : 08 07 06 05 04 03 02 01 00 Don't Care Bank 1 DRAM1 ID1 Bank 1 DRAM1 ID0 Bank 1 DRAM0 ID1 Bank 1 DRAM0 ID0 Bank 0 DRAM1 ID1 Bank 0 DRAM1 ID0 Bank 0 DRAM0 ID1 Bank 0 DRAM0 ID0 ML013316 9–10 Nbus
PAGE 209
Table 9–4 Presence Detect Bit PD Bit <3:0> PD 4-1 Description PD Bits 4321 Configuration (Parity/ECC) DRAM Organization RE Address CE Address Refresh Periods (ms) Normal Slow <4> <6:5> <7> PD 5 PD 7-6 PD 8 0100 1M x 72/80 1M x 4/16 10 10 16 128 0101 2M x 72/80 1M x 4/16 10 10 16 128 1011 4M x 72 4M x 4 12 11 64 256 1011 4M x 80 4M x 4 12 10 64 256 Controls data mode access, according to the following values: PD5 Definition 0 Fast page 1 Fast page with EDO C
PAGE 210
Table 9–5 ID Bits Bit ID Bit Description <6,4,2,0> ID 0 Used to define memory DIMM configuration (see Table 9–6). <7,5,3,17> ID 1 Sets the refresh mode, according to the following values: 0 Normal 1 Self refresh Table 9–6 Memory DIMM Configuration Bit PD8 IDO Description 1 0 x64 1 1 x72 Parity 0 0 x72 ECC 0 1 x80 ECC 9.2.
PAGE 211
These registers are read/pseudowritable registers located at a fixed address on Nbus in PCI I/O address space. Register 1 is located in Nbus offset 0x80A but is also aliased in two longwords at 0x80E and 0x82E. The register contains four reset status bits and one diagnostics in progress (DIP) bit. In reset reason register 3, at 0x82E, any write operation sets <4:0>. This is for testing only.
PAGE 212
Table 9–7 (Cont.) Reset Reason Registers Field Name Type Description <2> VME reset 0x80A : R/W to clear 0x80E : Read Only 82E : R/W to set If set, it indicates that the module received a VME reset. <3> Power-up 0x80A : R/W to clear 0x80E : Read Only 82E : R/W to set If set, all other bits are ignored. <4> DIP 0x80A : Read Only 0x80E : Read Only 82E : R/W to set If set, Digital Alpha VME 4 does not reset. 9.2.
PAGE 213
Figure 9–9 Module Control Register 1 31 08 07 06 05 04 03 02 01 00 MOD_CNTRL_REG_1 : Don't Care Timer 0 Mode Enable Undefined Watchdog Reset Enable Undefined Flash Switch Flash Write Enable Flash Select Flash Address 20 ML013289 Table 9–8 Module Control Register Field Name <1:0> Flash Address 20 Flash Select Type Description Divide flash ROM into four 1 MB windows. Flash Select divides the ROM into two 2 MB segments and Flash Address 20 divides the segments in half.
PAGE 214
Table 9–8 (Cont.) Module Control Register Field Name <5> Watchdog Timer Reset Enable Type When 0, watchdog timer expiration has no effect. If set, and the DIP bit of the reset reason register is cleared, a watchdog timer expiration generates a hardware reset of the module. Reset default is disabled. <6> <7> Description Undefined/reserved Timer 0 Mode 1 Enable Default at power-up is 0. When 0, Timer 0 in the 82C54 can only operate in modes 0 and 3.
PAGE 215
Table 9–9 Bcache Size and Speed Decode <2> <1> <0> Bcache Size Bcache Speed 0 0 0 Disables Bcache 0 0 1 512 KB 15 ns 0 1 0 2 MB 12 ns 0 1 1 Reserved for future use 1 0 0 Reserved for future use 1 0 1 Reserved for future use 1 1 0 Reserved for future use 1 1 1 Reserved for future use 9.3 ROM The system has two ROM structures: • Serial ROM (SROM) Contains 8 KB of code serially loaded into the 21064A chip’s internal cache (Icache) on power-up.
PAGE 216
Figure 9–11 Flash ROM Layout/Addressing ROM_BASE_ADDR : <00> Start of Console Firmware 512 KB Start of User Flash 512 KB <01> 1 MB <10> 1 MB <11> 1 MB ML013291 The flash ROM can be rewritten. To protect the flash ROM from unauthorized /accidental updates, a hardware switch must be closed before write operations are enabled. The switch, DIP switch 2 on the Digital Alpha VME 4 assembly, must always be open unless flash ROM is going to be updated.
PAGE 217
Channel B is uncommitted and uninitialized by system firmware. For more information about these serial lines, see Chapter 2. 9.4.2 Super I/O Register Address Space CPU Address: 0x1C0003E00 - 0x1C0007FE0 Nbus offset: 0x01F0 - 0x03FF Table 9–10 lists the base address values for the serial port and parallel port controller. The general registers are located at addresses 398 (index address) and 399 (data address). For example, writing an index value of 1 to address 398 selects the function address register.
PAGE 218
Table 9–10 (Cont.
PAGE 219
Table 9–10 (Cont.) Super I/O Register Address Space Map Address Offset Read/Write Physical Address Register 3BC-R/W 1 C000 7780 Data register 3BD-R 1 C000 77A0 Status register 3BE-R/W 1 C000 77C0 Control register 3BF 1 C000 77E0 None (tristate bus) Parallel Port Registers Table 9–11 lists the addresses for the integrated device electronics (IDE) registers.
PAGE 220
Table 9–12 lists the register and memory addresses for the keyboard/mouse controller. Table 9–12 Keyboard and Mouse Controller Addresses Offset Physical Address Register 60-R 1 C000 0C00 Auxiliary/keyboard data 60-W 1 C000 0C00 Command data 64-R 1 C000 0C80 Read status 64-W 1 C000 0C80 Command 9.6 TOY Clock The TOY clock function maintains the timekeeping information: year, month, date, day, hour, minute, second, 1/10th of a second, and 1/100th of a second.
PAGE 221
9.6.1 TOY Clock Timekeeping Registers CPU Address: 0x1C0100000 - 0x1C01FFFE0 Nbus offset: 0x8000 - 0xFFFF Time information is contained in eight 8-bit read/write registers offset from the base address: Table 9–13 TOY Clock Timekeeping Registers Field Register Description <0:3> TOY_BASE_ADDR+00 0.00 sec <4:7> 0.
PAGE 222
Field Register Description <7> TOY_BASE_ADDR+09 Enable Oscillator bit. Enables/disables the TOY clock chip’s internal oscillator. Use it to conserve the lithium source during transport, storage, or during any long period of non-use. When clear, the TOY clock operates. When set, the internal oscillator is disabled (factory default). These registers are not used: TOY_BASE_ADDR+03 TOY_BASE_ADDR+05 TOY_BASE_ADDR+07 9.6.
PAGE 223
Table 9–14 (Cont.) TOY Clock Command Register Field Name Type <2> Description Not used <3> Watchdog Timer Enable R/W <4> Pulse/Level O/P R/W <5> Watchdog Timer Assertion R/W <6> Watchdog Timer Select R/W <7> Transfer Enable R/W Enables/disables changes to the values in the timekeeping registers. When clear, the current value in the readable registers is frozen even though the internal timing continues.
PAGE 224
Table 9–15 Timer Interface Registers Field Register TMR_BASE_ADDR = 4000 Description <7:0> TMR_BASE_ADDR+00 Timer#0 Register TMR_BASE_ADDR+04 Timer#1 Register TMR_BASE_ADDR+08 Timer#2 Register TMR_BASE_ADDR+0C Control Register TMR_BASE_ADDR+10 Interrupt Status Register TMR_BASE_ADDR+14 Interrupt Status Register To program the timer device for initialization or during normal operation, the control byte (TMR_BASE_ADDR + 0x0C) is written.
PAGE 225
Table 9–16 Interval Timing Control Register Field <7:6> Name Type Description Specifies which timer is to be configured by this control byte. When set to ‘‘11’’, the control byte is a status read command, not a Timer Control operation. As a status read command, the control byte can be used to freeze the state of the timers for readback.
PAGE 226
Figure 9–14 82C54 Timer Data Access Data Rd/Wr (byte) No Mode 01 or 11? Yes LSB No Mode 11? "Signal Done" Yes Data Rd/Wr (byte) MSB ML013296 9.7.2 Timer Registers Each timer element is a 16-bit synchronous down counter. The device asserts or pulses the corresponding output pin when a counter reaches a 0 count. The following timers are identical in function but are fully independent: • Timer #0 must be clocked externally by P2 pin C13. Optionally, its gate input can also be driven by P2 pin C14.
PAGE 227
interrupt request (IRQ). The IRQ can be dismissed by an access to the timer interrupt status register. 9.7.
PAGE 228
The timer output is initially high. When the timer value is written, the output is driven low. The counter decrements to 0 where it drives the output high. • Mode 1 - Hardware Retriggerable One-Shot This mode allows a value to be written to the timer that can be used when a hardware trigger has been received. TMR_MAJOR_IP L (P2 pin C14) transitions from a high to a low.
PAGE 229
9.7.4 Interrupts The expiration of timers #0 and #2 are recorded in a timer status register. The asserted state of either or both of the timer status bits can be enabled to assert an interrupt request. The active low outputs of timer #1 and #2 are routed to P2 connector pins. The active low clock and gate inputs of timer #0 are also tied to P2 connector pins.
PAGE 230
The Timer IRQ line is asserted for a low-to-high transition of a timer’s output pin when that timer is enabled in the CSR to cause an interrupt. The interrupt is held asserted until the timer status summary register is read (clear on read). The corresponding timer expiration status bit is always set by a low-to-high on the timer output but this only causes the IRQ line to be asserted if the corresponding interrupt enable bit is set. In addition, the output of timer #1 is brought to the VIC IRQ <3>.
PAGE 231
Table 9–18 (Cont.) Timer Interrupt Status Register Field Name Type <1> <2:3> Description Timer #2 status When clear, the IRQ is dismissed. The bit is cleared at the end of the read cycle of a read operation originating from TMR_BASE_ ADDR+14. A read operation from TMR_BASE_ ADDR+10 has no effect. Not used <4> Read Status of Timer #0 IRQ Enable. When set, the timer output line has made an active transition. <5> Read Status of Timer #2 IRQ Enable.
PAGE 232
(general-purpose registers (GPRs), and so forth) at the time the watchdog timer expires before the full hardware reset. Watchdog timer operation is controlled by four registers - three in the DS1386 chip and a single enable bit in the module control register. Operation of the watchdog timer must be configured in the TOY clock command register (TOY_ BASE_ADDR+0x0B) and enabled in the module control register (MOD_CNTRL_ REG).
PAGE 233
Table 9–19 Watchdog Timer TOY Clock Command Register Field Name Type <0> <1> Description Not used Watchdog timer flag R/W <2> Not used <3> Watchdog timer enable R/W <4> Pulse/level O/P R/W <5> Watchdog timer assertion R/W <6> Watchdog timer select R/W <7> Transfer enable R/W See description of TOY clock.
PAGE 234
9.9 Nonvolatile RAM Digital Alpha VME 4 offers just under 32 KB of battery backed-up on-board SRAM. The RAM is provided by the DS1386 chip and is held nonvolatile by the built-in lithium battery source. The memory is read/write accessible in Nbus space. In effect, the DS1386 chip (TOY clock, watchdog timer, and NVRAM) contains 32 KB read/write byte elements. The lowest 14 of these bytes have special register functions for operation of the TOY clock and watchdog timer.
PAGE 235
10 VME Interface The VME interface handles the VMEbus and its interactions with the PCI bus. This chapter describes the functions of the VME interface, which are controlled by the operating system. See the documentation for the operating system for instructions on configuring the VME interface. The VME interface consists of the DC7407 chip, the VIC64 chip, the CY7C964 bus interfaces, and the connectors to the VMEbus on the backplane. Figure 10–1 shows a block diagram of the VME interface.
PAGE 236
The VME interface serves the following purposes: • As a VMEbus master, it controls PCI bus-to-VMEbus, or outbound, transactions • As a VMEbus slave, it handles VMEbus-to-PCI bus, or inbound, transactions and interprocessor communication. • It can be configured as the VME system controller, handling functions such as arbitration of bus ownership. • It handles interrupts to the VMEbus, as an interrupter and an interrupt servicing agent.
PAGE 237
Figure 10–2 shows a mapping of Window_1 and Window_2. Figure 10–2 Mapping Window_1 and Window_2 512 MB Window_1 64 MB Window_2 S/G 255 S/G 0 ML013378 Each page can be mapped to any one of the three VMEbus address spaces: A32, A24, or A16. As shown in Figure 10–3, numerous pages can be mapped to the same VMEbus address to allow access to the same location with different modes. The address modifier code is fully programmable for each page.
PAGE 238
Figure 10–3 Mapping Pages From PCI to VME PCI VME 4 GB Mem Space A32 Scatter-Gather Mapping A24 512 MB 2048 x 256K Pages A16 ML013377 10.1.1 Outbound Scatter-Gather Mapping The outbound scatter-gather entries control and map all master accesses from Digital Alpha VME 4 to the VMEbus. Figure 10–4 shows an outbound scattergather entry and how the VMEbus address is formed from the VME page and the PCI address.
PAGE 239
Figure 10–4 Outbound Scatter-Gather Entry 31 VME Addr <31:0> 18 17 o/b VME Page <31:18> 31 PCI Addr <28:18> 02 01 00 PCI Addr <17:2> 18 17 o/b VME Page 14 13 12 11 10 09 08 X 00 06 05 04 00 MBZ Function Code <2:1> Address Size <1:0> RMW Swap <2:0> Mode Valid ML013328 A PCI memory access in either VME WINDOW_1 or VME WINDOW_2 address windows causes a lookup for the corresponding scatter-gather entry.
PAGE 240
10.1.1.1 Address Modifier The scatter-gather entry has two fields that provide the address modifier used in the master VMEbus transfer. The address size (ASIZ) and function code (FC) fields map directly to the VME interface controller’s input for ASIZ and FC. Table 10–1 shows the use of these fields.
PAGE 241
The two accesses are handled as an indivisible sequence on the VMEbus by acquiring VMEbus ownership for the current access and holding it until another master operation is done by the processor. This is designed for doing atomic VMEbus RMW cycles. The VIC interface configuration register must be programmed with VIC_ ICR<7:5> = 001. A value of VIC_ICR<7:5> = 000 disables the RMW mode regardless of the setting in the scatter-gather map, while any other VIC_ ICR<7:5> value gives UNPREDICTABLE results.
PAGE 242
Because the VMEbus specification prohibits crossing any 256/2 KB boundaries, any DMA must split into a number of bus transfers. At the interval between these transfers, the VME interface can be programmed to wait a period of time before arbitrating again for the VMEbus and proceeding. This delay gives slave accesses to the Digital Alpha VME 4 the opportunity to complete during a blockmode transfer. This interleave period is programmable in the VIC block transfer control register, shown in Figure 10–5.
PAGE 243
• Source address • Destination address The mapping of PCI memory to VMEbus addresses is handled as usual through the scatter-gather mapping mechanism, however, the address modifiers in the mapping entry are automatically transformed to generate the block-mode version of the specified address modifier code (except for user-defined address modifier codes). The following sequence of steps set up a master DMA: 1. Write the DMA transfer length to the VME byte length registers, VIC_ BTLR0, VIC_BTLR1.
PAGE 244
Incoming slave accesses are mapped and controlled by two incoming scattergather maps: • For A32 accesses, a Digital Alpha VME 4 system occupies up to 128 MB of memory mapped by 16384 scatter-gather entries, each mapping an 8 KB page. • For A24 accesses, a Digital Alpha VME 4 system occupies up to 16 MB mapped by 2048 scatter-gather entries, each mapping an 8 KB page.
PAGE 245
VIF_ABR (VME_IF_BASE + 184) defines the base address of the Alpha VME 4 system in each VMEbus address space as shown in Figures 10–7 and 10–8. Figure 10–7 Address Decoding 31 24 23 16 15 08 07 00 VME A32 Addr VME A24 Addr VME A16 Addr = Region of address which can be compared to form base address ML013341 Associated with each of the top three comparison bytes is a bit mask to control the number of bits that are checked during a VMEbus address match.
PAGE 246
10.2.2 Inbound Scatter-Gather Entries The inbound scatter-gather RAM format is shown in Figure 10–9 and described in Table 10–3.
PAGE 247
Table 10–3 (Cont.) VME Address Field Name Description <13:12> Page Monitor Specifies how a Digital Alpha VME 4 system checks the scattergather entry for access, according to the following values: 0 No monitoring of the page. 1 Each time the page is accessed, Monitor 1 is incremented. 2 Each time the page is accessed, Monitor 2 is incremented. 3 Each time the page is accessed, Monitor 3 is incremented.
PAGE 248
Table 10–5 VME Interface Processor Page Monitor CSR Field Name Description <2:0> Monitor 1 Number of access to page. <3> Overflow Overflow for Monitor 1. When a counter overflows, it sets a bit in VIP_BESR register. If enabled by the VIP_ICR register, the overflow causes VIP_LIRQ<0> interrupt to be asserted at VIC_LIRQ<2>. <6:4> Monitor 1 Number of access to page. <7> Overflow Overflow for Monitor 1 <10:8> Monitor 1 Number of access to page. <11> Overflow for Monitor 1 Overflow 10.2.
PAGE 249
Because the global switches are meant to be issued to several modules, the slave targets of a global switch access do not acknowledge the cycle, but rather the master driving the write data transfer acknowledgements (DTACKs) the cycle itself (the VIF_ABR should be set to generate a self-access by the global-switch write). A write to an even address clears the selected switch and a write to an odd address sets the switch.
PAGE 250
Table 10–6 (Cont.) Interprocessor Communication Register Map Through VIF_ ABR + Register Interprocessor communication registers (ICR) 07 8-bit general-purpose register 3 R/W 09 8-bit general-purpose register 4 R/W 0B VIC revision register Read-only. Provides VIC64 hardware revision. 0D VIC status register Read-only. Provides VIC64 status revision. 0F Intercommunication register status Bits <4:0> are set when there is a write access to the corresponding ICR.
PAGE 251
Table 10–6 (Cont.) Interprocessor Communication Register Map Through VIF_ ABR + Register Interprocessor communication module switches (ICMS) Write-only. A write to an odd address sets the switch; a Write to an even address clears that switch. 020 Clear module switch 0 021 Set module switch 0 022 Clear module switch 1 023 Set module switch 1 024 Clear module switch 2 025 Set module switch 2 026 Clear module switch 3 027 Set module switch 3 10.
PAGE 252
10.3.1 Arbitrating the VMEbus 10.3.1.1 Requesting the VMEbus Three arbitration schemes — priority, round-robin, and single-level — are achieved by a combination of setting the arbiter/requester configuration register (VIC_ABR, offset 0xB0) and using the VMEbus request lines. See Table 10–7 and Figure 10–11. The granting of ownership of the VMEbus to a master is passed down the VMEbus along a daisy-chain.
PAGE 253
Table 10–7 Arbiter/Requester Configuration Register Field Name Description <3:0> Fairness timeout The fairness timeout field accepts the following values: <4> Not used <6:5> Request level <7> 0 Fair request is not enabled. Non-zero Number of 2-microsecond intervals that make up the fairness timeout period. F Fairness timeout period is not enabled, that is, the Digital Alpha VME 4 system can only request the VMEbus if no other requests for the VMEbus are being asserted.
PAGE 254
In addition to these four bus release modes, the scatter-gather RMW bit (RMC) can be used to force Digital Alpha VME 4 to hold ownership of the VMEbus for two accesses before releasing in the programmed ROR, RWD, or ROC fashion. See Section 10.1.2 for details.
PAGE 255
Table 10–8 (Cont.) VIC Release Control Register Field Name Description <7:6> Release protocol Specifies the release mode, according to the following values: 00 Release-on request (ROR) the Digital Alpha VME 4 system keeps ownership until another device requests the bus. 01 Release-when-done (RWD) the Digital Alpha VME 4 system releases the bus immediately after completion of the cycles for which it requested ownership.
PAGE 256
10.3.3.2 VMEbus Transfer Timers When enabled, the VME interface starts the transfer timer whenever the data phase of a cycle is signaled (DSx* asserting). If the timer expires before the data cycle is acknowledged or completes in error, the VME interface, as the system controller, flags a VMEbus error (asserting BERR*). This condition sets a status bit in the VMEbus error status register (VIC_BESR).
PAGE 257
Table 10–9 (Cont.) VMEbus Transfer Timeout Register Field Name Description <7:5> VMEbus timeout Specifies the timeout, according to the following values: 000 4 microseconds 001 16 microseconds 010 32 microseconds 011 128 microseconds 100 256 microseconds 101 512 microseconds 111 Disabled 10.3.3.3 Local Bus Transfer Timer When enabled, the local bus transfer timer starts whenever a data phase is initiated on the local bus (the bus between the VIC64 and DC7407).
PAGE 258
Figure 10–14 VIC Interrupt Request/Status Register 31 08 07 06 05 04 03 02 01 00 VME_IF_BASE + 80 : Don't Care VIC_VIRSR IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 Enable(1)/Disable(0) ML013345 Table 10–10 VIC Interrupt Request/Status Register Field Name <0> Description Controls whether the IRQs are reset or asserted. When <0> = 1, setting any of the bits <7:1> asserts the corresponding IRQ. When <0> = 0, setting any of the bits <7:1> clears the corresponding IRQ.
PAGE 259
Figure 10–15 VMEbus Interrupt Vector Base Registers 31 08 00 Don't Care Status/ID Vector ML013346 A local interrupt can be generated to the CPU by the VME interface when it detects a VMEbus IACK cycle for a VME interrupt that is pending. This interrupt can be used to inform system software that the VMEbus interrupt request has been serviced. The VIC interrupter interrupt control register (VME_IF_BASE + 0x00) provides enabling of priority encoding for this interrupt (Figure 10–16).
PAGE 260
10.4 Byte Swapping The Digital Alpha VME 4 interface provides hardware to support byte-swapping for transfers to and from the VMEbus. Four modes of swapping are supported. The swap mode is defined for each inbound or outbound page by the related scatter-gather entry. 10.4.1 DC7407 Byte Swapping The swap mode for each scatter-gather entry is defined by 3 bits, SWP<2:0>. Bits <1:0> define mode 0 through 3 and SWP<2> enables D64 swapping, which is only used in D64 block mode data transfers.
PAGE 261
Figure 10–17 Swap Modes Mode 0: No swap D32 11 00 Mode 1: Byte swap D32 00 11 10 01 10 01 01 10 01 10 00 11 00 Big Endian Byte Add. Little Endian Byte Add. D0 Little Endian Byte Add. Mode 2: Word swap D32 11 D0 Big Endian Byte Add. Mode 3: Longword swap D32 00 11 10 01 10 01 01 10 01 10 11 00 Big Endian Byte Add. Little Endian Byte Add. 11 00 D0 Little Endian Byte Add.
PAGE 262
Figure 10–18 Big Endian VME Byte Lane Formats A31 byte 0 byte 1 byte 2 A0 byte 3 D31 byte 4 byte 5 byte 6 D0 byte 7 byte 0 byte 1 byte 2 byte 3 byte 1 byte 2 byte 3 byte 1 byte 2 byte 1 byte 2 byte 0 byte 0 byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 3 ML013371 The longword transfers, tribyte transfers, and unaligned word transfers all use the byte lanes in the same way.
PAGE 263
Table 10–13 PCI BE# to Local A1,0 and SIZ1,0 Translation for Various Swap Modes PCI BE# <3:0> Mode 0 No Swap A1,0 SIZ1,0 Mode 1 Byte Swap A1,0 SIZ1,0 Mode 2 Word Swap A1,0 SIZ1,0 Mode 3 Longword Swap A1,0 SIZ1,0 1111 No cycle No cycle No cycle No cycle 1110 00 01 L 01 01 L 10 01 11 01 1101 01 01 L 00 01 L 11 01 10 01 1011 10 01 11 01 00 01 L 01 01 L 0111 11 01 10 01 01 01 L 00 01 L 00 10 10 10 1100 00 10 1001 01 10 L Noncontig Noncontig 0011
PAGE 264
Table 10–14 Local Bus A1,0 and SIZ1,0 to PCI BE# Translation Local Bus A1,0 SIZ1,0 Data Mode 0 BE# Mode 1 BE# Mode 2 BE# Mode 3 BE# 00 00 D[31:0] 0000 0000 0000 0000 00 11 D[31:8] 1000 0100 0010 0001 01 11 D[23:0] 0001 0010 0100 1000 00 10 D[15:0] 1100 1100 0011 0011 01 10 D[23:8] 1001 0110 0110 1001 10 10 D[15:0] 0011 0011 1100 1100 00 01 D[15:8] L 1110 1101 1011 0111 01 01 D[7:0] L 1101 1110 0111 1011 10 01 D[15:8] 1011 0111 1110 1101
PAGE 265
The windows defined by these registers must not overlap each other. The following sections describe these registers and the region of address space they define. Table 10–15 Access to PCI Memory Addresses Register PCI Configuration Address Space Purpose VME_CSR_BASE 00000810 This register gives access to the DC7407, VIC64, and CY7C964 registers when the base address of a window in PCI memory space is written into the register.
PAGE 266
The scatter-gather RAM is an 32K n longword page in memory space. The top 27 bits are read/write; the remaining 5 bits are MBZ. Scatter-gather RAM is not initialized by hardware and starts up in a random state. Firmware must initialize this area to a default state before using the VME subsystem. The scatter-gather RAM is fully programmable over the PCI bus. The mapping of the scatter-gather RAM takes up 128 KB of PCI memory space and has its own base address.
PAGE 267
DMASICR Bits 2-0 Local IPL setting for end of DMA interrupt. Bits 6-3 Reserved, must read as 1s. Bit 7 End of DMA interrupt mask bit. LICR1-7 Bits 2-0 Local IPL setting for LIRQ interrupt line. Bit 3 Indicates voltage level at LIRQ pin. Bit 4 Autovector enable. Must be set in the Digital Alpha VME 4 system. Bit 5 Edge/level enable for LICR2 and LICR7. Must be clear in the Digital Alpha VME 4 system. Bit 6 Polarity set for LICR2 and LICR7. Must be clear in Digital Alpha VME 4.
PAGE 268
Bits 7-2 User defined. Combines with ICMS switch number to provide vector. LIVBR Bits 1-0 Read only. Bits 7-2 User defined. Combines with LIRQ number to provide vector. EGIVBR Bits 1-0 Read only. Bits 7-2 User defined. Combines with fixed codes to provide vector. ICFSR Bits 3-0 Module switches. Bits 7-4 Global switches. ICR0-4 General-purpose registers. Accessible over the VMEbus or local bus. ICR5 Read-only register containing the VIC64 revision. Accessible over VMEbus or local bus.
PAGE 269
Bit 0 Set to include VMEbus acquisition time in local bus timeout. Bit 1 When VME interface is used as system controller, this bit is set to indicate arbitration timeout. Bits 4-2 Recommended timeout period for local bus is 64 µs (011). Bits 7-5 Recommended timeout period for VMEbus is 128 µs (100). The use of timeout periods depends on the VME environment.
PAGE 270
Bits 6,5 VMEbus request level. Bit 7 Arbitration mode. AMSR Defines response top and generation of user-defined address modifier codes. BESR All 8 bits are flags set by the VIC after status conditions that must be cleared by the processor. DMASR Bit 0 Block transfer in progress. Once set, must be cleared by processor. Bit 1 LBERR during DMA transfer. Bit 2 BERR during DMA transfer. Bit 3 Local bus error. Bit 4 VMEbus BERR. Bits 5,6 Reserved, read as 1s.
PAGE 271
Bits 3-0 Interleave period. Recommend a value of 0xF. Bit 4 Data direction bit: 0=write, 1=read. Bit 5 MOVEM enable. Recommend this be clear. Bit 6 BLT with local DMA enable. Bit 7 Module based DMA transfer enable. BTLR1-0 Registers for block transfer length for local DMA block mode transfers. SRR System reset register. 10.
PAGE 272
Table 10–16 (Cont.) VME_IF_BASE + A8 VIC_BTDR Block transfer definition register AC VIC_ICR Interface configuration register B0 VIC_ARCR Arbiter/requester configuration register B4 VIC_AMSR Address modifier source register B8 VIC_BESR Bus error status register BC VIC_DMASR DMA status register C0 VIC_SS0CR0 Slave select 0/control register 0 The D32 enable must be set in VIC_SS0CR0.
PAGE 273
Table 10–16 (Cont.
PAGE 274
10.7 VME Subsystem Restrictions (as of 03-Jun-94) This section describes limitations on the use of the VME subsystem due to outstanding hardware constraints. The intention is that these will be eliminated as new revision hardware components become available. This section will be updated as restrictions change. Please contact your field application engineer for the latest status on these constraints. 10.7.
PAGE 275
11 System Interrupts 11.1 System Interrupts Figure 11–1 shows a schematic overview of the interrupt structure in the Digital Alpha VME 4 system. Most interrupts are routed through the VIC64 chip, the Digital Alpha VME 4 interrupt controller, and the SIO chip. The 21064A receives six interrupts (CPU_IRQ[5:0]). The six interrupts are identical, asynchronous, level sensitive, and can be masked by PALcode individually. Table 11–1 lists the CPU interrupt assignments during normal operation.
PAGE 276
Figure 11–1 Block Diagram of the Interrupt Logic DC7407 (VIP) VIPSTATUS IRQ VIPERROR IRQ Interrupt Priority Lines VIC64 VME_IRQ1 through VME_IRQ7 VME Connectors (Super I/O) IRQ <7:3> (Mouse) IRQ12 (Keyboard) KB_IRQ PCISERR HALT SIO VIC_IPL2 VIC_IPL1 XILINX Interrupt CPU_IRQ3 VIC_IPL0 Controller VME Reset Interval Timer IRQ Periodic RT Timer Timer #1 IRQ CPU_IRQ2 1 ms Heartbeat Timer PMC0 IRQA PMC1 IRQA PMC0 IRQB CPU_IRQ1 PMC1 IRQB PMC0 IRQC PMC1 IRQC PMC0 IRQD CPU_IRQ0 PMC1 IRQD SCSI IRQ Ethernet IRQ
PAGE 277
Each interrupt can be individually masked by setting the appropriate bit in the interrupt/mask register. Interrupts generated by the VMEbus subsystem also need to be masked in the VIC64 chip (see Section 11.1.2). An interrupt is disabled by writing a 1 to the desired position in the interrupt/mask register. An interrupt is enabled by writing a 0. The interrupt/mask register is write only. A read of the interrupt/mask register returns the state of the interrupts regardless of which mask bits are set.
PAGE 278
Figure 11–4 Interrupt/Mask Register #3 07 06 05 04 03 02 01 00 804 : PMC1 IRQ C PMC0 IRQ C PMC1 IRQ B PMC0 IRQ B SCSI IRQ ETHER IRQ SIO IRQ VME IPL3 ML013319 Figure 11–5 Interrupt/Mask Register #4 07 02 01 00 803 : Reserved PMC1 IRQD PMC0 IRQD ML013321 11.1.2 VIC64 Chip System Interrupt Controller The Digital Alpha VME 4 system’s use of the VIC64 chip as an interrupt controller is modified slightly by the operation of the DC7407, the SIO chip, and the interrupt/mask registers.
PAGE 279
11.1.2.1 Basic Operation The VIC64 chip handles 19 interrupt sources. Each of these can be individually programmed to any of the seven IPLs in the controller’s interrupt control registers (ICRs). The generic form of the ICR is shown in Figure 11–6. Figure 11–6 Generic ICR 31 08 07 06 03 02 01 00 Don't Care Disable Encoded Priority 1-7 ML013305 A fixed relative ranking for requests is defined.
PAGE 280
Table 11–2 VIC64 Chip Interrupt Ranking RANK Interrupt Description CSRs 19 DC7407 Error VIC_LICR7, VIC_LIVBR 18 VME Interface Status/Error VIC_EGICR, VIC_EGIVBR 17 not used 16 not used 15 not used 14 not used 13 DC7407 Status 12 not used 11 Interprocessor Communications Global Switch VIC_ICGSICR, VIC_ICGSIVBR 10 Interprocessor Communications Module Switch VIC_ICMSICR, VIC_ICMSIVBR 9 VMEbus IRQ7* VIC_IRQ7ICR 8 VMEbus IRQ6* VIC_IRQ6ICR 7 VMEbus IRQ5* VIC_IRQ6ICR 6 VMEbus I
PAGE 281
Each of the these interrupt sources has an associated ICR that allows the interrupt to be programmed with an individual IPL or to be disabled. Figure 11–7 shows these ICRs. Figure 11–7 Device ICRs 31 08 07 06 03 02 01 00 Don't Care Disable Encoded Priority 1-7 ML013305 The vectors associated with these seven interrupt inputs have a single common root that is modified to give a unique vector for each device.
PAGE 282
Figure 11–9 VME IRQ* ICRs 31 08 07 06 03 02 01 00 Don't Care Disable Encoded Priority 1-7 ML013305 Table 11–3 VME IRQ ICR Priority Assignments Address Register Line :VME_IF_BASE+04 VIC_ICR1 1RQ1 :VME_IF_BASE+08 VIC_ICR2 IRQ2 :VME_IF_BASE+0C VIC_ICR3 IRQ3 :VME_IF_BASE+10 VIC_ICR4 IRQ4 :VME_IF_BASE+14 VIC_ICR5 IRQ5 :VME_IF_BASE+18 VIC_ICR6 IRQ6 :VME_IF_BASE+1C VIC_ICR7 IRQ7 Within the system, VMEbus interrupts compete (based on IPL and ranking) with other system interrupts.
PAGE 283
• DMA completion • VMEbus IACK cycle in response to a VMEbus interrupt generated by an Alpha VME system These conditions are divided into three cases. The first ‘‘case’’ is DMA completion. There is an ICR associated with this event, VIC_DMASICR (see Figure 11–10), which allows the signaling of DMA completion. If enabled, an interrupt is generated at the programmed IPL upon DMA completion.
PAGE 284
Figure 11–11 VIC Error Group ICR 31 VME_IF_BASE + 48 : 08 07 06 05 04 03 02 00 Don't Care VIC_EGICR ACFAIL* Interrupt Mask Write Post Fail Interrupt Mask Arb. Timeout Interrupt Mask SYSFAIL* Interrupt Mask SYSFAIL* Asserted IPL for this group of Interrupts ML013310 Finally, a local (on-board) interrupt is generated by the VIC64 chip when the VME interface detects a VMEbus IACK cycle to itself.
PAGE 285
Figure 11–13 VIC Error Group Interrupt Vector Base Register 31 VME_IF_BASE + 58 : VIC_EGVIBR 08 07 06 05 04 03 02 01 00 Don't Care User Programmable Vector-Base 000 ACFail 001 Write Post Fail 010 Arb. Timeout 011 SYSFAIL 100 VMEbus IACK Received 110 DMA Completion ML013312 11.1.4 SIO Chip Programmable Interrupt Controller The 82378 chip is used to deliver interrupts from the mouse, keyboard, and Super I/O chip (37C665) to the interrupt/mask register.
PAGE 286
11.1.4.2 NMI Status and Control Register Figure 11–14 shows the NMI status and control register. Figure 11–14 NMI Status and Control Register 31 08 07 06 05 04 03 02 01 00 Don't Care SERR # Status HALT Status Ignore on read HALT Enable SERR Enable Ignore on read ML013458 Table 11–4 contains more details about the settings in the NMI status and control register.
PAGE 287
Table 11–4 (Cont.) NMI Status and Control Register Bits Field Name Type Description <3> HALT Enable R/W When set to a one, HALTs are disabled and the halt status bit in this register is cleared. When cleared (reset default), HALTs are enabled as NMI events. <2> SERR Enable R/W When set to a 1, SERR reporting is disabled and the SERR status bit in this register is cleared. When cleared (reset default), SERRs are enabled as NMI events. <1:0> - R/W Ignore on read. Writes must be 0.
PAGE 288
The VMEbus SYSRESET* assertion generates a module reset only if Switch 3 is closed. This prevents a module configured as a VME system controller from locking into a reset state when it issues a VME SYSRESET* under software control. If Switch 3 is open, the VIC64 chip still resets (all internal registers return to their default state, current transactions are aborted) but the module reset is not generated.
PAGE 289
12 Console Primer This chapter describes the Digital Alpha VME 4 console and explains how to use basic commands to perform console tasks. The console achieves much of its power and flexibility from its traditional UNIX functionality. This chapter gives you an understanding of the basic functions of the UNIX like kernel, various utilities and tools, the user interface, and how these compare with the structure of the OpenVMS operating system.
PAGE 290
• Self-test diagnostics and extended functional diagnostics. You use UNIX command methods to combine these tools to solve complex problems. The UNIX command methods are piping, I/O redirection, commandlevel scripting, and control functions. Because the console is built around a multitasking kernel, it can support more complex functions, such as systems exercisers, the Maintenance Operations Protocol (MOP) listener, and remote console operations.
PAGE 291
12.1.3 Shell Operators The UNIX command line makes use of some Bourne shell operators to complete a command. In OpenVMS, some commands take parameters. The shell operators are similar but are much more powerful because you can use them to combine commands. These operators are described in Table 12–2. Table 12–2 Console Shell Operators Operator Name Description > Output creation Writes output to a specified destination, such as a file.
PAGE 292
Table 12–2 (Cont.) Console Shell Operators Operator Name Description ( ),{} Grouping Shows which commands are grouped together in complex command lines. These operators override the [precedence] of pipe, sequence, and background operators. Form: {cmd1 ; cmd2} | cmd3 *,?,[...] Pattern specifiers Like OpenVMS wildcard characters. Used for matching patterns in character strings. * matches any character or characters or none ? matches any single character [...
PAGE 293
• if command_sequence then command_sequence [ elif command_sequence then command_sequence ] [ else command_sequence ] fi Conditional branching in if, while, and until loops is determined by the exit status of the command sequence following the control structure. In general, an exit status of zero indicates success and results in the execution of the true path. In the following example, the eval command is used to extract an exit status from variable junk.
PAGE 294
Command Description Example show pal Displays version number of PALcode VMS PALcode V5.56-4, OSF PALcode X1.45-8 show device Displays known devices on system dkb0.0.0.1.0 DKB0 RZ57 mke0.0.0.4.0 MKE0 TZ85 eza0.0.0.6.0 EZA0 08-00-2B-19-60-31 ezb0.0.0.7.0 EZB0 08-00-2B-1A-2C-06 p_a0.7.0.0.0 Bus ID 7 p_c0.7.0.2.0 Bus ID 7 pkb0.7.0.1.0 PKB0 SCSI Bus ID 7 pke0.7.0.4.0 PKE0 SCSI Bus ID 7 The command show config displays all of this information. 12.
PAGE 295
>>> help examine deposit NAME examine FUNCTION Display data at a specified address. SYNOPSIS examine [-{b,w,l,q,o,h,d}] [-{physical,virtual,gpr,fpr,ipr}] [-n ] [-s ] [:]
NAME deposit FUNCTION Write data to a specified address. SYNOPSIS deposit [-{b,w,l,q,o,h}] [-{physical,virtual,gpr,fpr,ipr}] [-n ] [-s ] [:]
The help command supports a type of wildcarding.
PAGE 296
The examine and deposit commands manipulate devices to get access to data within the system. The default device is physical memory. When another device is specified, that device becomes the default. A default device is sticky, that is, all subsequent commands affect that device until another device is explicitly specified and becomes the new default. The console uses drivers as the mechanism for referring to various devices.
PAGE 297
12.4.1 Accessing Memory Commands are available for gaining access to memory. Note Because the console itself and other critical data structures reside in memory, be careful not to alter them. Use the alloc command to find an unused 1000-byte block of memory, as shown in the following example: >>> alloc 1000 03FFF000 The address of the allocated block is, in this case, 0x03FFF000. Use your allocated block to test the procedures in this section.
PAGE 298
An alternate method for dumping memory (or other devices or files) is the hex dump command, hd. The -l option specifies the number of bytes to display. Note Both -l and -n have the same result, but -l only works with hd and -n only works with examine. The distinction is caused by the commands; examine is a VMS like command and hd is a UNIX cloned command. >>> hd pmem:3fff000 -l 10 # Dump the allocated memory.
PAGE 299
>>> e r0 gpr: 0 ( # Examine R0 symbolically,... R0) 0000000000000002 >>> e gpr:0 gpr: 0 ( #...explicitly as device offset,... R0) 0000000000000002 >>> e 0 gpr: 0 ( # ...or implicitly as device offset. R0) 0000000000000002 >>> e 8 gpr: 8 ( # Examine R1... R1) 000000000000C408 >>> e gpr: 10 ( # ...and the next R2. R2) 0000000000000000 >>> e ipr:0 ipr: 0 ( # Examine an IPR... ASN) 0000000000000000 >>> e ipr: # ...and the next... 1 ( ASTEN) 0000000000000000 >>> e + ipr: # ...and the next...
PAGE 300
12.5 Using Pipes and grep to Filter Output To search for specific values in a device, use a pipe with the grep command. A pipe ( | ) enables the output of one command to be the input for the next command without creating an intermediate file. The grep command filters its input according to the command argument. Because the grep command requires input, a pipe is used to channel the output of the examine command into the grep command. The following example uses grep to search for a pattern in memory.
PAGE 301
>>> ls foo foo no such file # Check to see if foo exists. >>> e 3fff000 -n 1 > foo >>> ls foo foo # Redirect examine output to file foo. # Check to see if foo exists. >>> cat foo pmem: 3FFF000 0000000000000000 pmem: 3FFF008 0000000000000000 >>> rm foo >>> ls foo foo no such file # Display foo. # Delete (remove) file foo. # Check to see if foo exists. 12.
PAGE 302
>>> ps ID PCB Pri CPU Time Affinity CPU -------- -------- --- -------- -------- --0000006c 001423a0 3 2 00000001 0 0000005c 00144b40 2 19253 00000001 0 0000005b 00147a60 2 9 00000001 0 00000059 0014c060 2 21750 00000001 0 00000058 0014edc0 2 5 00000001 0 00000056 00152860 2 3 00000001 0 00000055 00153ae0 2 2 00000001 0 00000054 00181580 2 6 00000001 0 0000004f 00154d60 5 38 ffffffff 0 . . .
PAGE 303
To add another command to the script, use the append operator, >>. If the command you are appending contains characters that could be interpreted by the echo command, use a grouping character to enclose the appended command. The following example uses the single quote ’ grouping character to prevent the command-separator character ( ; ) in the appended command from terminating the echo command.
PAGE 304
$ create sample. show version ls -l sample (Control-Z exit) $ 2. Make the file compatible with the MOP load protocol. To accomplish this, run the add_header.exe program to append a one-block header to the file, making it compatible with the MOP load server. This executable program is on the Firmware Update CD at [ALPHAVME]ADD_HEADER.EXE. If you prefer, copy the file to the SYS$LOGIN area and define it as a foreign command, for example, addhead.
PAGE 305
>>> cat sample show version ls -l sample >>> sample version rwx- rd V1.
PAGE 306
Table 12–3 Digital Alpha VME 4 Console Command Summary Command Options Parameters VMS like Console Commands boot [-file filename] [-flags root,bitmap] [-halt] [ boot_device ] deposit [-{b,w,l,q,o,h}] [-n val] [-s val] [ device:]address data examine [-{b,w,l,q,o,h,d}] [-n val] [-s val] [ device:]address help initialize [command] [-c] [-d device_path] [slot-id] show { envar, config, device, error, hwrpb, memory} start address UNIX like Console Commands cat chmod file...
PAGE 307
Table 12–3 (Cont.) Digital Alpha VME 4 Console Command Summary Command Options Parameters UNIX like Console Commands rm file... set envar value sleep time sort tr file... [-{c | d | s}] string1 [string2] uniq wc file... [-{l | w | c}] file...
PAGE 308
Table 12–3 (Cont.
PAGE 309
13 Console Commands Console mode provides the user interface that you enter when the power-on self-test (POST) completes. The console prompt is: >>> Console mode is entered in any of the following ways: • You press the Halt/Reset switch on the front panel. Depending on your operating system and applications running at the time, this could damage application files. • The module receives a VMEbus reset signal and switch 3 of the configuration switches on the Digital Alpha VME 4 module is enabled.
PAGE 310
• Ctrl/S—Suspends output to the console terminal • Ctrl/Q—Resumes output to the console • Ctrl/C—Aborts the current command, if possible The console program has no control over this once control has been passed to another program such as an operating system or loadable diagnostic. • Ctrl/R—Retypes the current command line • Ctrl/O—Causes the console code to throw away output characters rather than send them to the terminal Entering another Ctrl/O resumes sending output characters.
PAGE 311
13.1.4 Console Command Dictionary The following commands are supported by the Digital Alpha VME 4 console program.
PAGE 312
alloc alloc — allocate a block of memory Exports the malloc routine out to the shell so you can allocate a block of memory from heap. You can then use the block simultaneously with several test routines (there can be several readers but only one writer). Syntax alloc size [modulus] [remainder] [-flood] [-z heap_address] Arguments size Specifies the size (hexadecimal) in bytes of the requested block. modulus Specifies the modulus (hexadecimal) for the beginning address of the requested block.
PAGE 313
alloc See Also dynamic, free Console Commands 13–5
PAGE 314
boot boot — bootstrap the system Initializes the processor, loads a program image from the specified boot device, and transfers control to that image. If you do not specify a boot device, the default boot device, defined by the value of the BOOTDEF_DEV environment variable, is used. You can specify a list of devices so that a bootstrap is attempted from each device in order. When one of the devices boots successfully, control passes to that booted image.
PAGE 315
boot A 300-byte database in the same format as the BOOTP message is used to store the received packet. Once a BOOTP packet is broadcasted and received, the database is marked as initialized, ending the first stage of the operation. 2. The client uses TFTP to obtain the image. TFTP takes the information in the BOOTP packet (or uses a file name specified in the command string or the environment variable BOOT_FILE and gets the file from the server.
PAGE 316
boot The file name defined by this environment variable becomes the file name in the outgoing BOOTP request packet. For example: >>> set ewa0_bootp_file /var/adm/ris/ris0.alpha/vmunix.old 5. Do not specify a file name: >>> boot ewa0 With this method, because none of the environment variables are written, the boot process runs through both stages. Any server that receives the request replies. In the client-server paradigm, the way the firmware acts is affected by the software running on the server.
PAGE 317
boot Environment Variable EWA0_INETADDR Field Description Internet address of the network interface (EWA0) Local address. TFTP and the Address Resolution Protocol (ARP) do not operate properly without the correct address. The address of a server, which may or may not be on the local network. Usually, this is the server from which to boot. This is the default remote host contacted by TFTP. The address of an Internet gateway on the local network.
PAGE 318
boot EWA0_DEF_SINETADDR EWA0_DEF_GINETADDR EWA0_DEF_SUBNETMASK EWA0_DEF_INETFILE These variables are defined in the following example: >>> >>> >>> >>> >>> >>> set set set set set set EWA0_DEF_INETADDR 16.123.16.53 EWA0_DEF_SINETADDR 16.123.16.242 EWA0_DEF_GINETADDR 16.123.16.242 EWA0_DEF_SUBNETMASK 255.255.255.0 EWA0_DEF_INETFILE bootfiles/vmunix EWA0_INET_INIT nvram Another way for the database to be initialized is when BOOTP is invoked, either explicitly or as a consequence of invoking TFTP.
PAGE 319
boot Protocol Drivers You normally use BOOTP and TFTP to bootstrap across a network. However, you can invoke the protocols as protocol drivers. The BOOTP and TFTP protocols must be followed by a network in the protocol tower. When a BOOTP request is broadcast, the environment variable EWA0_BOOTP_ SERVER is copied into the sname field of the request packet and the variable EWA0_BOOTP_FILE is copied into the file field of the request packet.
PAGE 320
boot Arguments boot_device A device path or list of devices from which the firmware attempts to boot, or a saved boot specification in the form of an environment variable. Use the set command with the environment variable BOOTDEF_DEV to define the default boot device. You can specify a list of devices by using commas without spaces. For example: >>> set BOOTDEF_DEV ewa0,dka0 Options -file filename Specifies the name of a file to load into the system.
PAGE 321
boot 4. >>> boot -fi //usr//local//bootfile//alphavme_v1_1-0 -protocol bootp ewa0 The system performs a TCP/IP BOOTP network boot from Ethernet port EWA0. 5. >>> boot -flags 0,1 The system boots from the default boot device using boot flag settings 0,1. 6. >>> boot -halt dka0 The system loads the operating system from the SCSI disk, dka0, but remains in console mode.
PAGE 322
break break — break from a program loop Breaks from a for, while, or until loop. Exits the current shell with a status or returns the status of the last command. Syntax break [break_level] Arguments break_level Specifies the status code to be returned by the shell.
PAGE 323
cat cat — copy files Concatenates files that you specify to the standard output. If you do not specify files on the command line, the cat command copies standard input to standard output. You can also copy or append one file to another by specifying I/O redirection. Syntax cat [-l length] file1 [file2 . . . ] Arguments file1 [file2 . . . ] Specifies the name of the input files to be copied. Options -l length Specifies the number of bytes (decimal) of each input file to copy. Examples 1.
PAGE 324
chmod chmod — change file attributes Changes the specified attributes of a file. The chmod command is a subset of the equivalent UNIX command. Syntax - chmod + = {r,w,x,b,z} file1 [file2 . . . ] Arguments file1 [file2 . . . ] Specifies the files or inodes to be modified. Options – A minus sign indicates to remove the specified attributes. + A plus sign indicates to add the specified attributes.
PAGE 325
chmod Examples 1. >>> chmod +x script Adds the executable attribute to the file, script. 2. >>> chmod =r errlog Sets the file errlog to read only. 3. >>> chmod -w dk* Makes all SCSI disks nonwriteable.
PAGE 326
chown chown — change ownership of memory block Changes the ownership of a memory block to the specified process. Syntax chown pid address1 [address2 . . . ] Arguments pid Specifies the hexadecimal process identifier (PID) of the new owner. You can display PIDs with the ps command. address1 [address2 . . . ] Specifies the hexadecimal address or list of addresses of allocated blocks for which ownership is to be changed.
PAGE 327
clear clear — delete environment variable Deletes an environment variable from the name space. Note Some environment variables, such as BOOTDEF_DEV, are permanent and cannot be deleted. Syntax clear variable_name Arguments variable_name Specifies the name of the environment variable to be deleted. Example >>> clear foo >>> Deletes the environment variable foo.
PAGE 328
clear_log clear_log — clear error log in NVRAM Clears and initializes the area of NVRAM used for console error logging. The entire area of NVRAM where fault information is stored is cleared to zero. Miscellaneous pointers, counters, and initialization flags used in the error logging process are reset accordingly. Notes The current contents of the NVRAM error log area is destroyed and lost forever. If you do not want the console to prompt you before the log areas is cleared, specify the -nc command option.
PAGE 329
date date — display or change time Displays or modifies the current date and time. If you include no arguments, the command displays the current date and time. If you do include arguments, the command modifies the current date and time stored in the time-of-year (TOY) clock. Note The date is not preserved if the TOY clock battery has been disabled with the set TOY SLEEP command. On the next power-on of the module, the battery is reenabled and the date might need to be reinitialized.
PAGE 330
date Example >>> date 199208031029.
PAGE 331
deposit deposit — write memory data Writes data to a memory location, a register, a device, or a file. After initialization, if you have not specified a data address or size, the default address space is physical memory, the default data size is a quadword, and the default address is zero. You specify an address or device by concatenating the device name with the address, for example, pmem:0, and by specifying the size of the space to which to write.
PAGE 332
deposit fpr: ipr: pt: pcicfg: pcidmem: pcismem: pciio: eerom: ferom: toy: Floating-point register set. The data size defaults to quadword. The following symbols for address are recognized: f0, f1, . . . f31. Internal processor register set. The size defaults to quadword. The following symbols for address are recognized: ps, asn, asten, astsr, at, fen, ipir, ipl, mces, pcbb, prbr, ptbr, scbb, sirr, sisr, tbchk, tbia, tbiap, tbis, esp, ssp, usp, and whami.
PAGE 333
deposit + - * @ Names the location immediately following the last location referenced in an examine or deposit. For references to physical or virtual memory, the location is the last address plus the size of the last reference. For other address spaces, the address is the last address referenced plus one. Names the location immediately preceding the last location referenced in an examine or deposit.
PAGE 334
deposit -physical The address space is physical memory. Using this option is the same as specifying the pmem: device. -virtual The address space is virtual memory. Using this option is the same as specifying the vmem: device. -gpr The address space is general purpose registers. Using this option is the same as specifying the gpr: device. -fpr The address space is floating-point registers. Using this option is the same as specifying the fpr: device. -ipr The address space is internal processor registers.
PAGE 335
deposit 4. >>> d -l -n 10 -s 200 pmem:0 8 Deposits 8 into the first longword of each of the first 17 pages in physical memory.
PAGE 336
dynamic dynamic — show memory Shows the state of dynamic memory. Dynamic memory is split into two main heaps: the console’s private heap and the remaining memory heap. Syntax dynamic [-c [-r]] [-h] [-p] [-v] [-setsize] [-extend byte_count] [-z heap_address] Options -c Performs a consistency check on the default heap or the heap specified with option -z. -r Repairs a broken heap by flooding free blocks with DYN$K_FLOOD_FREE if and only if the free blocks have been corrupted.
PAGE 337
dynamic Examples 1. 2. 3.
PAGE 338
echo echo — display text output Sends a line of text that you enter on the command line to the current output device. The default output device is your console screen. The echo command separates arguments (words) in the line with blanks and adds a new line character to the end of the line. Whenever you specify pipes or I/O redirection, enclose the text within single quotes. Syntax echo [-n] args... Arguments args... Specifies the character strings to be displayed.
PAGE 339
echo 4. >>> echo > foo ’this is the simplest way _>to create a long file. All characters will be echoed _>to file foo until the closing single quote.’ >>> cat foo this is the simplest way to create a long file. All characters will be echoed to file foo until the closing single quote. >>> Shows how you can use echo to create a file that is several lines long.
PAGE 340
eval eval — evaluate expression Evaluates a postfix expression. Syntax eval 2 -ib 3 2 -b 3 64 -io 75 64 -o 75 operand1 operand2 operator -id -d -ix -x Arguments operand1 The first numeric value to be evaluated. operand2 The second numeric value to be evaluated. operator One of the following: • + Add the operands. • - Subtract operand2 from operand1. • * Multiply the operands. • / Divide operand1 by operand2. Options -ib Indicates that the operands are binary values.
PAGE 341
eval -b Displays the output as binary values. -o Displays the output as octal values. -d Displays the output as decimal values. -x Displays the output as hexadecimal values. Examples 1. >>> eval 5 10 + 15 The sum of 5 plus 10 is 15. 2. >>> eval -ix -d 5 10 + 21 The sum of 5 plus 0x10 is 21 (decimal).
PAGE 342
examine examine — display memory data Displays data located at a specified address: a memory location, a register, a device, or a file. After initialization, if you have not specified a data address or size, the default address space is physical memory, the default data size is a quadword, and the default address is zero. You specify an address or device by concatenating the device name with the address, for example, PMEM:0, and by specifying the size of the data to be displayed.
PAGE 343
examine vmem: gpr: fpr: ipr: pt: pcicfg: pcidmem: pcismem: pciio: eerom: ferom: toy: Virtual memory. All access and protection checking occur. If the access would not be allowed to a program running with the current PS, the console issues an error message. If memory mapping is not enabled, virtual addresses are equal to physical addresses. General purpose register set, R0-R31. The data size defaults to -q. Floating-point register set, F0-F31. The data size defaults to -q. Internal processor register set.
PAGE 344
examine ipr- name pt- name PC + - * @ Names an internal processor register. The size defaults to quadword; the address space defaults to ipr. The following symbols for name are recognized: ps, asn, asten, astsr, at, fen, ipir, ipl, mces, pcbb, prbr, ptbr, scbb, sirr, sisr, tbchk, tbia, tbiap, tbis, esp, ssp, usp, and whami. Names a PAL Temporary register. The data size defaults to quadword; the address space defaults to pt. The following symbols for name are recognized: pt0, pt1, . . . pt31.
PAGE 345
examine -o The data size is octaword. -h The data size is hexaword. -d The data displayed is the decoded macro instruction. Alpha instruction decode (-d) does not recognize machine-specific PAL instructions. -physical The address space is physical memory. Using this option is the same as specifying the pmem: device. -virtual The address space is virtual memory. Using this option is the same as specifying the vmem: device. -gpr The address space is general purpose registers.
PAGE 346
examine 2. >>> e -g 0 gpr: 0 ( R0) 0000000000000002 Examine GPR register R0 by address space (-gpr option). 3. >>> e gpr:0 gpr: 0 ( R0) 0000000000000002 Examine R0 by device name. 4. >>> examine pc gpr: 0000000F ( PC) FFFFFFFC Examine the program counter (PC). 5. >>> examine sp gpr: 0000000E ( SP) 00000200 Examine the GPR stack pointer (SP) register. 6.
PAGE 347
examine 11. >>> examine pmem: 20040048 DB MFPR S^#2B,B^48(R1) Look at the next instruction.
PAGE 348
exer exer — exercise devices Exercises one or more devices by performing read, write, and compare operations. Optionally, reports performance statistics. A read operation reads from a device into a buffer. A write operation writes from a buffer to a device. A comparison operation compares the contents of the two buffers. The exer command uses two buffers, buffer1 and buffer2. A read or write operation can be performed using either buffer. A compare operation uses both buffers.
PAGE 349
exer -eb end_block Specifies the ending block number (hexadecimal) within the file stream. The default is 0. -p pass_count Specifies the number of passes to run the exerciser. If you specify 0, the exerciser runs forever or until you enter Ctrl/C. The default is 1. -l blocks Specifies the number of blocks (hexadecimal) to exercise. This option has precedence over the -eb option. If only reading, and you specify neither l nor -eb, the exerciser reads until it reaches the end-of-file (EOF).
PAGE 350
exer n N c ? s Write without lock from buffer1 Write without lock from buffer2 Compare buffer1 with buffer2 Seek to file offset prior to last read or write First, seek to a random block offset within the specified range of blocks. Next, call the program random to create each of a set of numbers once. Then, choose a set that is a power of two and is greater than or equal to the block range. Each call to random results in a number that is then mapped to the set of numbers in the block range.
PAGE 351
exer Description Exercises one or more devices. As described in the preceding overview section, the exer command uses two buffers, buffer1 and buffer2. The buffers are in main memory in the memory zone heap. Both buffer1 and buffer2 are initialized to a data pattern before any I/O operations occur. These buffers are never reinitialized, even after completing one or more passes. The data patterns with which the buffers are initialized are 0x5A in every byte of each buffer.
PAGE 352
exer You can use a random number generator to seek to varying device locations before performing either a read or write operation. Randomization is achieved by calling the function random, which uses a linear congruential generator (LCG) to generate the numbers. This algorithm is not truly random, but it comes closest to meeting the needs of the exer command. Each time that random is called, it returns a number from a specified range.
PAGE 353
exer The exer command returns an error code immediately after a read, write, or compare error, if the D_HARDERR environment variable is set to HALT. When an error occurs and continue or loop on error is specified, then subsequent operations specified by the action string option occur except for comparisons. For instance, if a read error occurs, a subsequent comparison is skipped since a read failure preceding a compare operation guarantees that the comparison fails.
PAGE 354
exer 5. >>> exer -eb 64 -bc 4 -a ’?w-Rc’ dka0 A destructive write test over block numbers 0 through 100 on disk dka0. The packet size is 2048 bytes. The action string specifies the following sequence of operations: 1. Set the current block address to a random block number on the disk between 0 and 97. A four block packet starting at block numbers 98, 99, or 100 would access blocks beyond the end of the length to be processed so 97 is the largest possible starting block address of a packet. 2.
PAGE 355
exer 7. >>> set myd 0 >>> exer -bs 1 -bc a -l a -a ’w’ -d1 ’myd myd ~ =’ foo >>> clear myd >>> hd foo -l a 00000000 ff 00 ff 00 ff 00 ff 00 ff 00 .......... Use an environment variable myd as a counter. Write 10 bytes of the pattern ff 00 ff 00... to RAM disk file foo. A packet size of 10 bytes is used. Because the length specified is also 10 bytes, only one write occurs. Delete the environment variable myd. The hd, hexadecimal dump of foo shows the contents of foo after the exer command is run. 8.
PAGE 356
exer See Also memexer 13–48 Console Commands
PAGE 357
exit exit — exit current shell Exits the current shell with the specified status or returns the status of the last command executed. Syntax exit exit_value Arguments exit_value Specifies the status code to be returned by the shell. Examples 1. >>> exit Exits returning the status of the previously executed command. 2. >>> exit 0 Exits with success status. 3. >>> test || exit Runs test and exits if there is an error.
PAGE 358
false false — return failure status Returns a failure status.
PAGE 359
free free — deallocate memory Frees a block of memory that has been allocated from a heap. The block is returned to the appropriate heap. Syntax free address1 [address2 . . . ] Arguments address1 address2 . . . Specifies an address (hexadecimal) or list of addresses of allocated blocks to be returned to the heap.
PAGE 360
grep grep — search for regular expressions Globally searches for regular expressions and prints any lines containing occurrences of the regular expressions. A regular expression is a shorthand way of specifying a wildcard type of string comparison. Since the grep command is line oriented, it only works on ASCII files. Syntax grep [-c] [-i] [-n] [-v] f expression -f file g [file1] [file2 . . . ] Arguments expression Specifies the regular expression for which to search.
PAGE 361
grep + ? \ x’ Repeated matching. When placed after a pattern, the plus sign indicates that the pattern should match one or more times. For example, [0-9]+ matches any sequence of one or more digits. Optional matching. When placed after a pattern, the question mark indicates that the pattern can match zero or one times. For example, [a-z][0-9]? matches a lowercase letter alone or followed by a single digit. Prevents the character (denoted by x) following the backslash from having special meaning. file..
PAGE 362
grep 2. >>> alloc 20 00FFFFE0 >>> deposit -q pmem:fffff0 0 >>> e -n 3 ffffe0 pmem: FFFFE0 EFEFEFEFEFEFEFEF pmem: FFFFE8 EFEFEFEFEFEFEFEF pmem: FFFFF0 0000000000000000 pmem: FFFFF8 EFEFEFEFEFEFEFEF >>> e -n 3 ffffe0 | grep -v 0000000000000000 pmem: FFFFE0 EFEFEFEFEFEFEFEF pmem: FFFFE8 EFEFEFEFEFEFEFEF pmem: FFFFF8 EFEFEFEFEFEFEFEF >>> free ffffe0 >>> The grep command searches for all quadwords in a range of memory that are non-zero.
PAGE 363
hd hd — dump file contents Dumps the contents of a file in hexadecimal and ASCII format. Syntax hd [-{byte | word | long | quad}] file... Arguments file... Specifies the files to be displayed. Options -byte Prints data in bytes. -word Prints data in words. -long Prints data in longwords. -quad Prints data in quadwords. Examples 1. 2.
PAGE 364
hd 3. >>> -word foo 00000000 6874 2065 7571 6369 206B 7262 776F 206E the quick brown 00000010 6F66 2078 756A 706D 6465 6F20 6576 2072 fox jumped over 00000020 6874 2065 616C 797A 6420 676F the lazy dog 4.
PAGE 365
help help— help on commands Defines and shows the syntax for each command that you specify on the command line. If you do not specify a command, the help command displays information about itself and lists the commands for which additional information is available. For each argument (or command) on the command line, the help command tries to find all topics that match that argument.
PAGE 366
help 2. >>> help * # List all topics and associated text. Requests help on all topics. 3. >>> help ex Requests help on all commands that begin with ‘‘ex’’. 4. >>> help boot Requests help on the boot command.
PAGE 367
init_ev init_ev — initialize environment variables Sets all environment variables to their default values. Once you issue this command, you need to reset the system or issue the init command to set the environment variables to their default values. Syntax init_ev Example >>> init_ev Note: A System Reset or init command must be issued immediately after this command to set all environment variables to their default values!! >>> A system reset or the init command is now required.
PAGE 368
initialize initialize — initialize the console, a device, or the processor Initializes the console, a device, or the processor. Syntax init[ialize] [-c] [-d device] Options -c Specifies that the console be initialized. -d device Specifies a device to be initialized. Examples 1. >>> init Initializes the processor. 2. >>> initialize -d ewa0 Initializes device EWA0.
PAGE 369
kill kill — delete process Deletes the processes listed on the command line. Processes are killed by making a call to a kernel function with the process ID (PID) as the argument. Syntax kill pid1 [pid2 . . . ] Arguments pid1 pid2 . . . Specifies the PIDs of the processes to be killed. You can display PIDs with the ps command. Example >>> memtest -p 0 & >>> ps | grep memtest 000000f1 00217920 2 >>> kill f1 >>> ps | grep memtest 9357 ffffffff 0 memtest ready Runs memtest.
PAGE 370
line line — read a line Copies one line (up to a new line) from the standard input channel of the current process to the standard output channel of the current process. This command always writes at least a new line as output. Use this command in scripts to read from the user’s terminal, or to read lines from a pipeline while in a for/while/until loop. Syntax line Examples 1.
PAGE 371
ls ls — list files Lists files or inodes in the system. Inodes are RAM disk files, open channels, and some drivers. RAM disk files include script files, diagnostics, and executable shell commands. Syntax ls [-l] [file1] [file2 . . . ] Arguments file1 file2 . . . Specifies the files or inodes to be listed. If you omit the argument, the command lists all files and inodes on the system. Options -l Lists the files or inodes in long format. Each file or inode is listed on a line with additional information.
PAGE 372
memexer memexer — memory exerciser Starts a specified number of graycode memory test processes running in the background. Each test randomly allocates and tests blocks of memory twice the size of the Bcache, using all available memory. The pass count is 0 to run the tests forever. Nothing is displayed unless an error occurs. Syntax memexer [number_of_tests] Arguments number_of_tests Specifies the number of memory test processes to start. The default is 1.
PAGE 373
memtest memtest — memory test Tests memory with any or all of four tests: Test Description Graycode memory test Writes, reads, and verifies a graycode pattern and an inverse graycode pattern for the specified address range. Writes, reads, and verifies a marching pattern and an inverse marching pattern for the specified address range. Exercises random addresses within the specified range with random data of random length.
PAGE 374
memtest 2. Reads each location, verifies the data, and writes the inverse of the data. The read-verify-write is done one longword at a time. This causes the following: • All data bits are written as a one and zero. • All but one data bit toggle between longword writes. • Address shorts are identified. 3. Reads and verifies each location. To verify that sections of the second and third loops are not performed, use the -f (fast) option.
PAGE 375
memtest The random test: 1. Obtains an address index into the Linear Congruential Generator (LCG) structure that is dependent on the specified length. The test obtains the data index as a function of the entered random data seed and the maximum 32 bit data pattern. 2. Calls the random number generator, using the address index and an initial address seed of 0, to obtain a random address. 3.
PAGE 376
memtest If you issue a Ctrl/C or the kill command with a PID in the middle of testing, the memtest process might not abort right away. To increase speed of execution, check for a Ctrl/C or kill command done outside of any test loops. If this is not satisfactory, you can run concurrent memtest processes in the background with shorter lengths within the target range.
PAGE 377
memtest -rs random_seed Specifies the random seed. Use this option only with the -rb option. The default is 0. -rb Specifies to randomly allocate and test all of the specified memory address range. Allocations are done of block_size. -f Specifies fast mode. If you specify -f, the data comparison is omitted. Only ECC /EDC errors are detected. -m Specifies that the memory test is to be timed. At the end of the test, the elapsed time is displayed. By default, the timer is off.
PAGE 378
memtest -g Specifies a group name. Currently, the only group supported is MFG. -se Specifies a soft error threshold. Examples 1. >>> memtest -sa 200000 -l 1000 Tests memory starting at 0x200000 (-sa) for 0x1000 bytes (-l). 2. >>> memtest -sa 200000 -l 1000 -f Tests memory from 0x200000 for 0x1000 bytes, but data is not verified (-f). 3. >>> memtest -sa 300000 -p 10 Writes a default block size of 8192 bytes from 0x300000 for 10 passes (-p). 4.
PAGE 379
memtest See Also memexer Console Commands 13–71
PAGE 380
net net — MOP function Using a specified port, performs basic maintenance operations protocol (MOP) operations. The net command performs basic MOP operations, such as, loopback, request IDs, and remote file loads. The net command also provides the means to observe the status of a network port. Specifically, the net command with the -s option displays the current status of a port including the contents of the MOP counters. This is useful for monitoring port activities and trying to isolate network failures.
PAGE 381
net -l0 Sends an Ethernet loopback to a specified destination node. You specify the address of the destination node with the -da option. -l1 Requests a MOP loopback. -rb Requests to be rebooted by sending a MOP V4 request boot message to a remote boot node. You specify the address of the destination node with the -da option. -csr Displays the values of the Ethernet port CSRs. -els Enables the extended design verification test (DVT) loop service. -kls Kills the extended DVT loop service.
PAGE 382
net -lw wait_in_secs Waits the specified number of seconds for the loop messages from the -l1 option to return. If the messages do not return in the specified time period, an error message is generated. -sv mop_version Sets the preferred MOP version number for operations. Valid values are 3 or 4. Examples 1. >>> net -sa -ewa0: 08-00-2b-1d-02-91 Displays the local Ethernet port station address. 2.
PAGE 383
ps ps — show process Displays the system state in the form of process status and statistics.
PAGE 384
pwrup pwrup — run power-on diagnostics Runs the power-on diagnostics script. The pwrup command initializes network environment variables and runs memory tests. Syntax pwrup Example >>> pwrup Runs the power-on script.
PAGE 385
rm rm — remove file Removes the specified files from the file system. Allocated memory is returned to the heap. Syntax rm file1 [file2 . . . ] Arguments file1 file2 . . . Specifies the files to be deleted. Example >>> foo >>> >>> foo >>> ls foo rm foo ls foo no such file Lists file foo to show that it exists, removes file foo, lists file foo again to show that it is gone.
PAGE 386
sa sa — set process affinity Changes the affinity mask of a process. The affinity mask of a process specifies the processors on which the process can run. Syntax sa process_id affinity_mask Arguments process_id Specifies the process ID (PID) of the process to be modified. affinity_mask Specifies the new affinity mask, which indicates on which processors the process can run. Bits 0 and 1 of the mask correspond to processors 0 and 1, respectively.
PAGE 387
semaphore semaphore — show system semaphores Shows all the semaphores known to the system by traversing the semaphore queue.
PAGE 388
set set — set environment variable Sets or modifies the value of an environment variable. Some of the environment variables are stored in nonvolatile memory. You use environment variables to pass configuration information between the console and the operating system. For a listing of predefined environment variables, see Table 3–2. Syntax set envar_name value [-default] [-integer] [-string] Arguments envar_name Specifies the name of the environment variable to be assigned a new value.
PAGE 389
set the factory to the device that contains the factory-installed software. For systems that do not ship with factory-installed software, the default setting is null. boot_file Sets the file name to be used when a bootstrap requires a file name. The default setting is null. boot_osflags Sets additional parameters to be passed to system software. The default setting is 0,0. Examples 1.
PAGE 390
set 5. >>> set AUTO_ACTION BOOT Sets the system’s default console action to boot after an error, halt, or power-on. 6. >>> set BOOT_FILE avme.sys Sets the file name to be used when the system’s boot requires a file name to avme.sys. 7. >>> set BOOT_OSFLAGS 0,1 Sets the system’s default boot flags to 0,1. 8. >>> set foo 5 Creates environment variable foo and sets its value to 5.
PAGE 391
set led set led — display char on LED Displays a character on the front panel light emitting diode (LED). Syntax set led char [-b] Arguments char Specifies the character to display on the front panel LED. Prefix metacharacters with a backslash (\). Options -b Specifies that the character be displayed in bright mode. The default is dim mode. Examples 1. >>> set LED "W" -b Displays an uppercase W on the LED panel at full brightness.
PAGE 392
set reboot srom set reboot srom — set reboot mode to Serial ROM Mini-Console Enters the Serial ROM (SROM) Mini-Console. The only valid (and necessary) argument is srom. When you issue this command, you enter the SROM Mini-Console the next time you reset or power on the system. Once issued, the command prevents you from rebooting from the console until you alter NVRAM bytes using the SROM Mini-Console. To alter the NVRAM bytes, enter the SROM Mini-Console command wb.
PAGE 393
set toy sleep set toy sleep — disable TOY clock’s internal oscillator Disables the DS1386 TOY clock’s internal oscillator, lengthening the shelf life of the device. When you execute this command, bit 8 of the MONTH register of the device is set to 1, disabling the TOY clock’s oscillator. The TOY clock’s time registers cease to advance, and the life of the device’s internal lithium battery is lengthened.
PAGE 394
sh sh — create new shell Creates another shell process. Each shell process implements most of the functionality of the Bourne shell. Syntax " -x # sh -v -d [-l] [-r] [-p] [arg . . . ] Arguments arg Specifies a text string terminated with white space. Options -v Prints lines as they are read. -x Shows commands just before they are executed. -d Deletes STDIN when the shell is done. -l Traces the lexical analyzer (shows tokens as they are recognized). -r Traces the parser (shows rules as they execute).
PAGE 395
sh Example >>> sh >>> # start a new shell # the new shell’s prompt >>> sh -v >> sh -x >> # all substitutions have been performed.
PAGE 396
show show — display system information Displays the current value of an environment variable or other system parameter. Syntax show [{config, device, hwrpb, led, map, mode, pal, version}] [envar_name] Arguments config Displays the system configuration. device Displays devices and controllers in the system. hwrpb Displays the Alpha hardware restart parameter block (HWRPB). led Displays a character illuminated on the LED panel. map Displays system virtual memory map.
PAGE 397
show Commonly Used Environment Variables auto_action Displays the console action following an error halt or power on. The action can be halt, boot, or restart. bootdef_dev Displays the device or device list from which bootstrapping is attempted. boot_file Displays the file name to be used when a bootstrap requires a file name. boot_osflags Displays the additional parameters to be passed to system software. language Displays the language in which system software and layered products are displayed.
PAGE 398
show config show config — display system configuration Displays the system configuration. Syntax show config Example >>> show config Digital Equipment Corporation Alpha VME 4/288 SRM Console V1.1-0 VMS PALcode V5.56-4, OSF PALcode X1.45-8 MEMORY: System Controller: 16 Meg of system memory VIC64 Enabled Hose 0, PCI slot 0 DECchip 7407 slot 1 DECchip 21040-AA ewa0.0.0.1.0 08-00-2B-E4-E3-06 slot 2 NCR 53C810 pka0.7.0.2.0 SCSI Bus ID 7 dka0.0.0.2.0 RZ26L dka300.3.0.2.0 RZ26L dka500.5.0.2.
PAGE 399
show device show device — displays devices Displays the devices and controllers in the system. By default, all devices and controllers that respond are shown. The device naming convention is as follows. dka0.0.0.0.
PAGE 400
show device 2. >>> show device e ewa0.0.0.6.0 EWA0 08-00-2B-1D-27-AA Displays devices that start with ‘‘e’’. 3. >>> show device *k* dkc0.0.0.2.0 mke0.0.0.4.0 # Show SCSI devices. DKC0 MKE0 RZ57 TLZ04 Displays all devices with ‘‘k’’ in the device name. 4. >>> show device dk dkc0.0.0.2.0 # Show SCSI disks. DKC0 RZ57 Displays all devices starting with ‘‘dk’’ (all SCSI disks). 5. >>> show device mk mke0.0.0.4.0 >>> # Show SCSI tape drives.
PAGE 401
show hwrpb show hwrpb — display HWRPB Displays the address of the Alpha hardware restart parameter block (HWRPB).
PAGE 402
show led show led — display LED character Displays the current character being displayed on the front LED panel. Syntax show led [-hex] Options -hex Displays the contents of the LED register. If you do not specify -hex, the character being displayed is echoed to the console. Examples 1. >>> show led Displays the current character being displayed by the LED panel. 2. >>> show led -hex Displays the contents of the LED register.
PAGE 403
show map show map — display memory map Displays the current system virtual memory map. Note The map is empty after all console initialization. To fill in the page table entries, enter the boot command with the -halt option at the console prompt.
PAGE 404
show_log show_log — display NVRAM error log information Displays console-detected fault information that was previously stored in the error log area of NVRAM. If you do not specify command-line options, the command displays the most recent fault. Console error logging is completely independent of the operating system’s error logging. Syntax " -n [count] # show_log -all -new Options -n count Displays the number of most-recent faults indicated by count that are logged into the NVRAM error log area.
PAGE 405
show_log 2.
PAGE 406
sleep sleep — suspend execution Suspends execution of a console process for a specified number of seconds. The console process temporarily wakes up every second to check for and kill pending bits. Syntax sleep [-v] time_in_secs Arguments time_in_secs Specifies the number of seconds to sleep. The default is one second. Options -v Specifies that the value supplied is in milliseconds. The default is 1000 (one second). Examples 1. >>> ((sleep 10; echo hi there)&) >>> (10 seconds expire...
PAGE 407
sort sort — sort a file Arranges the lines of a file in lexicographic order and writes the results to STDOUT. The size of the file that sort can handle is limited by the size of memory. Syntax sort file Arguments file Specifies the file to be sorted. Examples 1. >>> echo > foo ’banana _>pear _>apple _>orange’ Create file foo with 4 lines. 2. >>> sort foo apple banana orange pear Sort file foo and send output to the console.
PAGE 408
sp sp — set priority Modifies the priority of a process. Changing the priority of the process impacts the behavior of the process and the rest of the system. Syntax sp process_id new_priority Arguments process_id Specifies the process ID (PID) of the process to be modified. new_priority Specifies the new priority for the process. Priority values range from 0 to 7 where 7 is the highest.
PAGE 409
start start — start program Starts program execution at the specified address or starts drivers. Syntax start [-drivers [device_prefix]] [address] Arguments address Specifies the PC address at which to start execution. Options -drivers [device_prefix] Specifies the name of the device or device class to stop. If no device prefix is specified, then all drivers are started. Examples 1. >>> start 400 Starts program execution at address 400. 2. >>> start -drivers Starts all the drivers in the system.
PAGE 410
stop stop — stop CPU or device Stops the CPU or a specified device. Syntax stop [-drivers [device_prefix]] [processor_num] Arguments processor_num Specifies the processor to stop. If you use this argument, specify 0. Options -drivers [device_prefix] Specifies the name of the device or the device class to stop. If you do not specify a device prefix, the command stops all drivers. Example >>> stop Stops the processor.
PAGE 411
update update — update flash ROMs on the system Loads new firmware into the flash ROMs (FEPROMs). To modify the flash ROMs, you must close DIP switch #2 on the Digital Alpha VME 4 module. The update process proceeds as follows: 1. The image is loaded from the specified device into system memory. 2. A prompt appears for confirmation of update continuation. 3. The FEPROMS are reprogrammed. Each byte of the FEPROM is verified.
PAGE 412
update -target device Specifies the device that contains the FEPROMs to be upgraded. Valid targets are CONSOLE and USERFLASH. Examples 1. >>> update -fi alphavme_v1_1-0 -dev ewa0 -prot mop -tar console update -path mop:alphavme_v1_1-0/ewa0 -target console ..... Network load complete. Host name: OHMY Host address: aa-00-04-00-00-4b new: 1.
PAGE 413
update The program will take at most several minutes. Erasing the target flash device... ........ Erasure completed. Programming... ........ Programming completed Verifying... Update successful >>> The example above shows how to do an update using the TFTP protocol.
PAGE 414
PAGE 415
A Module Connector Pinouts Sections A.1 through Section A.5 provide pinout information for the Alpha VME 4: • CPU connector • I/O Type 1 card connector • Primary breakout module connector • Secondary breakout module connector • PMC I/O Companion card A.
PAGE 416
A.2.1 VMEbus (J1) Connector Pinouts Table A–1 lists the pinouts for the VMEbus (J1) connector (P2).
PAGE 417
Table A–1 (Cont.) VMEbus (J1) Connector Pin Row A Row B Row C 27 VCC VME_D28 PP_PE 28 Ground VME_D29 PP_BUSY 29 Ground VME_D30 PP_ACK_L 30 Ground VME_D31 PP_AFD_L 31 VCC Ground PP_INIT_L 32 VCC VCC PP_SLIN_L A.2.2 Console (J6) and Serial (J7) Connector Pinouts Table A–2 lists the pinouts for the console (J6) and serial (J7) connectors. Figure A–1 shows a pinout diagram.
PAGE 418
A.2.3 Ethernet (J9) Connector Pinouts Table A–3 lists the pinouts for the Ethernet (J9) connector. Figure A–2 shows a pinout diagram. Table A–3 Ethernet (J9) Connector Pinouts Pin Signal 1 transmit + 2 transmit - 3 receive + 4 no connection 5 no connection 6 receive - Figure A–2 Ethernet (J9) Connector Pinouts Pin 1 Pin 8 Front view mating side MLO-013550 A.3 Primary Breakout Module Connector Pinouts Table A–4 lists the pinouts for the primary breakout module (54-24663-01).
PAGE 419
Table A–4 (Cont.
PAGE 420
Figure A–3 Primary Breakout Module Connector Pinouts Side 1 J1 XP2 C32 B32 A32 C1 B1 A1 49 1 50 2 J2 (SCSI) Side 2 C1 B1 A1 C32 B32 A32 J3 C1 B1 A1 C32 B32 A32 J4 MLO-013551 A.4 Secondary Breakout Module Connector Pinouts Figure A–4 shows the layout of the pinouts for the secondary breakout module. Note the positions of the J1 (keyboard and mouse) and J6 (parallel port) connectors.
PAGE 421
Figure A–4 Secondary Breakout Module Connector Pinouts A1 A32 C1 C32 J2 14 26 1 13 J6 J1 2 4 2 4 J4 J5 1 3 1 3 P2 C1 B1 A1 C32 B32 A32 MLO-013552 Sections A.4.1 and A.4.2 provide more detail on the J1 and J6 connectors, respectively. A.4.1 Keyboard and Mouse (J1) Connector Pinouts Table A–5 lists the pinouts for the keyboard and mouse (J1) connector. Figure A–5 shows a pinout diagram.
PAGE 422
Table A–5 Keyboard and Mouse (J1) Connector Pin Signal 1 MOUSE_DATA 2 KBRD_DATA 3 Ground 4 VCC 5 MOUSE_CLOCK 6 KBRD_CLOCK Figure A–5 Keyboard and Mouse (J1) Pinouts 6 4 5 3 Front view mating side 2 1 MLO-013553 A.4.2 Parallel Port (J6) Connector Pinouts Table A–6 lists the pinouts for the parallel port (J6) connector. Figure A–6 shows a pinout diagram.
PAGE 423
Table A–6 (Cont.) Parallel Port (J6) Connector 9 PP_DATA7 10 PP_ACK_L 11 PP_BUSY 12 PP_PE 13 PP_SLCT 14 PP_AFD_L 15 PP_ERR_L 16 PP_INIT_L 17 PP_SLIN_L 18-25 Ground 26 N/C Figure A–6 Parallel Port (J6) Connector Pinouts J2 14 26 1 13 J6 Front view mating side MLO-013554 A.5 PMC I/O Companion Card Connector Pinouts Tables A–7 and Table A–8 list the pinouts for the PMC I/O Companion Card (54-24665-01) mouse (J2) and keyboard (J3) connectors, respectively.
PAGE 424
Table A–7 PMC I/O Companion Card Mouse (J2) Connector Pin Signal 1 MOUSE_DATA 2 KBRD_DATA 3 Ground 4 VCC 5 MOUSE_CLOCK 6 KBRD_CLOCK Table A–8 PMC I/O Companion Card Keyboard (J3) Connector Pin Signal 1 KBRD_DATA 2 MOUSE_DATA 3 Ground 4 VCC 5 KBRD_CLOCK 6 N/C Figure A–7 PMC I/O Companion Card Mouse (J2) and Keyboard (J3) Connector Pinouts 6 4 5 3 Front view mating side 2 1 MLO-013553 A–10 Module Connector Pinouts
PAGE 425
Index A ACFAIL* assertion, 11–8 Address mapping, 5–1 Address modifier, 10–6 Address space cacheable, 5–4 DECchip 21071-CA CSR, 5–4 DECchip 21071-DA, 7–7 DECchip 21071-DA CSR, 5–5 noncacheable, 5–4 of Nbus, 9–1 of PCI dense memory space, 5–14 of PCI host bridge CSRs, 7–7 of super I/O chip, 9–2 of super I/O register, 9–19 of VME interface, 10–2 PCI configuration, 5–8 decoding for primary bus configuration addresses in, 5–8 definition of, 5–8 PCI interrupt acknowledge/special cycle in, 5–5 PCI sparse I/O, 5–5
PAGE 426
BOOTED_FILE environment variable, 3–4 BOOTED_OSFLAGS environment variable, 3–4 BOOTP, 13–6 BOOT_DEV environment variable, 3–4 BOOT_FILE environment variable, 3–4 BOOT_OSFLAGS environment variable, 3–4 break command, 13–14 Breakout module installing, 2–1, 2–15, 2–18, 2–20 jumpers for, 2–17 setting jumpers, 2–19 Buffers memory DMA read, 6–31 memory DMA write, 6–31 memory I/O, 6–31 memory I/O write, 6–31 memory merge, 6–31 memory write, 6–32 Burst length of CPU-initiated transactions, 7–3 of DMA transactions,
PAGE 427
Commands (cont’d) exit, 13–49 false, 13–50 free, 13–51 grep, 13–52 hbeat_diag, 4–9 hd, 13–55 help, 13–57 i8254_diag with -t 1, 4–10 with -t 2, 4–11 with -t 3, 4–12 with -t 4, 4–13 with -t 5, 4–13 with -t 6, 4–14 initialize, 13–60 init_ev, 13–59 ioclrlock, 7–6 kill, 13–61 killing a process with, 12–14 line, 13–62 ls, 13–63 memexer, 13–64 memtest, 13–65 monitoring status with, 12–13 ncr810_diag with -t 1, 4–24 with -t 2, 4–24 with -t 3, 4–25 with -t 4, 4–25 with -t 5, 4–25 with -t 6, 4–25 with -t 7, 4–26 net,
PAGE 428
Connector pinouts (cont’d) I/O Type 1 card, A–1 keyboard and mouse, A–7 parallel port, A–8 PMC I/O companion card, A–9 primary breakout module, A–4 secondary breakout module, A–6 VMEbus, A–2 Connectors, 2–4 Console, 12–1 See also Commands cable, connecting, 2–21 code tests, 2–28 commands, 13–1 overview of, 12–2 connector pinouts, A–3 features, 12–1 help, 12–6 hybrid of UNIX and OpenVMS, 12–1 mode entering, 3–3 exiting, 3–3 POST descriptions, 4–5 prompt, invoking diagnostics from, 4–2 scripts, creating, 12–1
PAGE 429
DECchip 21040-AA, 8–3 See also Ethernet controller DECchip 21071-BA, 6–1 block diagram of, 6–30 DECchip 21071-CA, 6–1 block diagram, 6–2 CSR address space, 5–4, 6–8 functions, 6–3 DECchip 21071-DA See also PCI host bridge CSR address space, 5–5 CSR addresses, 7–7 Decoder logic, testing, 4–7 Delete key, 13–1 deposit command, 13–23 Device interrupt control registers, 11–7 Device interrupts, 11–6 Diagnostic commands ds1386_diag with -t 1, 4–18 with -t 2, 4–19 with -t 3, 4–20 with -t 4, 4–21 with -t 5, 4–21 ene
PAGE 430
Diagnostics (cont’d) NCR810 internal loopback test, 4–25 NCR810 interrupt test, 4–26 NCR810 PCI configuration register test, 4–24 NVRAM address-on-address test, 4–19 NVRAM march I test, 4–18 NVRAM march II test, 4–19 operating environments for, 4–1 POST, 4–1 POST memory diagnostic test, 4–7 POST NVRAM diagnostic test, 4–6 test descriptions, 4–5 to 4–30 test sequence (figure), 4–30 timer 0 loopback test, 4–12 timer 1 interrupt test, 4–14 timer 2 interrupt test, 4–13 timer 2 square wave test, 4–11 timer 2 ter
PAGE 431
D_OPER environment variable, 3–5 D_PASSES environment variable, 3–5 D_REPORT environment variable, 3–5 D_SOFTERR environment variable, 3–5 D_STARTUP environment variable, 3–5 D_TRACE environment variable, 3–5 E echo command, 13–30 ENABLE_AUDIT environment variable, 3–5 enet_diag command with -t 1, 4–22 with -t 2, 4–22 Environment variables, 3–3 setting, 13–80 Environmental specifications, 1–4 EPIC interrupt, 11–13 Error and diagnostic status register, 6–13 Error handling, memory, 6–32 Error high address re
PAGE 432
G General control register, 6–11 Global switches, 10–14 Global timing register, 6–27 grep command, 13–52 using pipe with, 12–12 H Halt switch, 3–2 Hardware retriggerable one-shot mode (1), 9–30 Hardware triggered strobe mode (5), 9–30 HAXR0 register, 5–5 HAXR2 register, 5–5 hbeat_diag, 4–9 hd command, 13–55 Heartbeat register, 9–14 timer test, 4–4, 4–9 help command, 13–57 Host address extension registers, 7–18 I I/O buffer, memory, 6–31 companion card See PMC I/O companion card module configuration switch
PAGE 433
Interval timing registers, 9–25 ioclrlock command, 7–6 iogrant signal, 7–6 ISA bus controller recovery timer register, 9–4 clock divisor register, 9–4 J Jumpers cache, settings of, 2–13 SCSI termination, 2–16 setting watchdog signal, 2–16 K Keyboard cables, connecting, 2–21 connector pinouts, A–7 controller, 9–21 Keys, console command, 13–1 kill command, 13–61 Kit contents, 2–1 L LAN address ROM test, 4–22 LAN address ROM verification test, 4–22 LANGUAGE environment variable, 3–6 LANGUAGE_NAME environmen
PAGE 434
memtest command, 13–65 Merge buffer, memory, 6–31 MODE environment variable, 3–6 dependence of diagnostic tests on, 4–7 Modes block data transfer, 10–7 continuous, square wave output (3), 4–11, 4–12, 4–14, 9–30 hardware retriggerable one-shot (1), 9–30 hardware triggered strobe (5), 9–30 interrupt on terminal count, 4–10, 4–13 single data transfer, 10–7 software retriggerable one-shot (0), 9–29 timer, 9–29 VMEbus swap, 10–26 Module clear heartbeat register, testing, 4–9 configuration register, 9–6 connector
PAGE 435
O Operating system, booting, 3–7 > operator, 12–12 Operators redirection operator, 12–12 shell, 12–3 Order numbers, 2–35 P Page monitor CSR, 10–13 PAL devices, testing, 4–10 environment variable, 3–6 Parallel interface, 1–2 Parallel port connector pinouts, A–8 Parity support, for PCI devices, 7–4 PCI bus, 8–1 addresses, decoding, 7–3 base registers, 5–15, 7–16 configuration address space, 5–8 decoding for primary bus configuration addresses in, 5–8 definition of, 5–8 configuration registers, 8–3, 8–7 contr
PAGE 436
PCI mezzanine card adapter, 8–11 PCI-to-physical memory addressing, 5–15 PD bits, 9–10 Performance, 1–2 Physical addresses, decoding of by PCI host bridge, 7–2 Physical specifications, 1–2, 1–4 Pinouts, A–1 console and serial connector, A–3 CPU connector, A–1 Ethernet connector, A–4 I/O Type 1 card connector, A–1 keyboard and mouse connector, A–7 parallel port connector, A–8 PMC I/O companion card connector, A–9 primary breakout module connector, A–4 secondary breakout module connector, A–6 VMEbus connector
PAGE 437
Registers (cont’d) dummy registers, 7–15 error and diagnostic status register, 6–13 error high address register, 6–19 error low address register, 6–18 examining, 12–7 general control register, 6–11 general interrupt control register, 11–5 global timing register, 6–27 HAXR0 register, 5–5 HAXR2 register, 5–5 heartbeat, 9–14 host address extension registers, 7–18 interrupt mask registers, 9–8, 11–3 interrupt registers, 9–8 interval timing control register, 9–26 interval timing registers, 9–25 ISA bus controlle
PAGE 438
Registers VIC (cont’d) local interrupt vector base register, 11–7 register, testing, 4–28 release control register, 10–20 VIP PCI configuration register testing, 4–28 VME interface base and mask register, 10–11 interprocessor communication registers, 10–14 processor page monitor CSR, 10–13 VME PCI configuration registers, 10–30 VMEbus interrupt request interrupt control registers, 11–7 interrupt vector base registers, 10–24 interrupter interrupt control register, 10–25, 11–10 transfer timeout register, 10–2
PAGE 439
show led command, 13–94 show map command, 13–95 show_log command, 13–96 Signal, iogrant, 7–6 Single mode data transfers, 10–7 SIO chip See Super I/O chip sleep command, 13–98 Slots, needed for installation, 2–6 Software retriggerable one-shot mode (0), 9–29 sort command, 13–99 sp command, 13–100 SROM, 9–17 initialization countdown, 4–4 tests, 2–27 start command, 13–101 Status display, 3–2 monitoring, 12–13 Status/error interrupts, 11–8 stop command, 13–102 Subsystems cache and memory, 6–1 components of, 6–1
PAGE 440
Timers (cont’d) VMEbus arbitration, 10–21 VMEbus timeout, 10–21 VMEbus transfer, 10–22 3 timers loopback test, 4–11 Timing register A, 6–25 Timing register B, 6–26 TLB data registers, 7–21 tag registers, 7–20 TOY clock, 9–22 bitwalk test, 4–20 command register, 9–24 diagnostic tests for, 4–3 register test, 4–3 registers, testing, 4–20 testing, 4–27 time advancement test, 4–21 timekeeping registers, 9–23 Transfer timers, 10–22, 10–23 Translated base registers, 7–15 Translation buffer invalidate all register,
PAGE 441
VME interface (cont’d) registers, summary of, 10–37 restrictions, 10–40 scatter-gather entry, outbound, 10–4 scatter-gather mapping, outbound, 10–4 single mode data transfers, 10–7 tests, 4–28 VME interrupt request interrupt control registers, 11–7 VME PCI configuration registers, 10–30 VMEbus, 1–2 ACFAIL* assertion, 11–8 arbitration, 10–18 control of, 10–17 schemes, 10–17 arbitration timeout, 11–8 arbitration timers, 10–21 connector pinouts, A–2 IACK cycle, 11–9 interrupt control, 10–17 interrupt handling
PAGE 442