User`s manual

CPU clock divisor jumpers, 2–7
CPU fan connector, 2–12
D
dc power distribution, 4–7
See also Power requirements
Debugging
native, 1–6
source-level, 1–6
Debug monitor, 3–9
code in flash ROM, 1–6
starting, 3–9
DECchip 21071-BA, 1–4
DECchip 21071-CA, 1–4
DECchip 21071-DA, 1–4
DECchip 21072 chipset, 1–1, 1–4
DECladebug, 1–6
Digital Semiconductor Information Line,
B–1
Diskette controller, 1–5
Diskette drive
connector, 2–10
Documentation, B–2
DRAM, 1–1
SIMM connectors, 2–10
Dynamic RAM
See DRAM
E
Enclosure fan connector, 2–13
Environmental characteristics, 5–2
F
Fan, heat sink, 3–3, 3–4, 3–6
Fan connectors
CPU, 2–12
enclosure, 2–13
Features, 1–1
Flash ROM, 4–9
access, 4–14
address bit 19, 4–14
enable/disable jumpers, 2–6
Flash ROM (cont’d)
header content, 4–9, 4–10
higher bank image selection, 4–12
jumper, 2–6
MAKEROM tool, 4–9
special headers, 4–9
structure, 4–12
TOY RAM location 3F, 4–12
update-enable jumper, 4–14
Floppy drive
See Diskette drive
G
GRAFOIL pad, 3–5
H
Hardware configuration jumpers, 2–6
Hardware requirements, 3–1 to 3–2
Heat sink, 3–3, 3–5
Heat sink fan, 3–3, 3–4, 3–6
I
IDE, 1–5
connector, 2–10
Industry Standard Architecture
See ISA
Integrated device electronics
See IDE
Interrupt
assignment, 4–3
control, 4–1
mask registers, 4–5
scheme, 4–1
sources, 4–4
Interrupt control and PCI arbitration logic
block diagram, 4–1
ISA
arbitration, 4–5
connectors, 2–9
devices, 4–6
interface overview, 1–5
Index–2