User`s manual

4.1 PCI Interrupts and Arbitration
Interrupt PLDs Function
The MACH210 PLD acts as an 8-bit I/O slave on the ISA bus at addresses
804h, 805h, and 806h. This is accomplished by a decode of the three ISA
address bits sa<2:0> and the three ecas_addr<2:0> bits.
Each interrupt can be individually masked by setting the appropriate bit in the
mask register. An interrupt is disabled by writing a 1 to the desired position
in the mask register. An interrupt is enabled by writing a 0. For example,
bit <7> set in interrupt mask register 1 indicates that the INTB2 interrupt is
disabled. There are three mask registers located at ISA addresses 804h, 805h,
and 806h.
An I/O read transaction at ISA addresses 804h, 805h, and 806h returns the
state of the 17 PCI interrupts rather than the state of the masked interrupts.
On read transactions, a 1 means that the interrupt source shown in Figure 4–2
has asserted its interrupt. The mask register can be updated by writing
addresses 804h, 805h, or 806h. The mask register is write-only.
Figure 4–2 Interrupt and Interrupt Mask Registers
RAZRAZRAZRAZRAZRAZRAZ intd3
76543210
LJ-04211.AI
Notes:
Interrupt and Interrupt Mask Register 3 (ISA Address 806h)
Interrupt and Interrupt Mask Register 2 (ISA Address 805h)
Interrupt and Interrupt Mask Register 1 (ISA Address 804h)
RAZ = Read-as-Zero, Read-Only
Interrupt Mask Register Is Write-Only
intb3intc0intc1intc2intc3intd0intd1intd2
76543210
inta0inta1inta2inta3intb0intb1intb2 sio
76543210
4.1.2 PCI/ISA Arbitration
Arbitration logic is implemented in the Intel 82378ZB Saturn IO (SIO) chip.
The arbitration scheme is flexible and software programmable. Refer to
the Intel 82420/82430 PCIset ISA and EISA Bridges document for more
information about programmable arbitration.
Functional Elements 4–5