User`s manual

4.1 PCI Interrupts and Arbitration

The AlphaPC64 interrupt controller has 17 interrupts: four from each of the

four PCI slots (16) and one from the SIO bridge.

All PCI interrupts are combined in the PLD and drive a single output signal,

pci_isa_irq. This signal drives CPU input cpu_irq0 through a multiplexer.

There is also a memory controller error interrupt and an I/O controller error

interrupt within the CPU.

Table 4–1 lists the CPU interrupt assignment during normal operation.

Table 4–1 CPU Interrupt Assignment

Interrupt

Source

CPU

Interrupt Description

pci_isa_irq cpu_irq0 Combined output of the interrupt PLD

rtc_irq_l cpu_irq1 Real-time clock interrupt from DS1287

nmi cpu_irq2 Nonmaskable interrupt from the SIO bridge

— cpu_irq3,

cpu_irq4

Not used; tied to ground

sys_irq0 cpu_irq5 Hardware interrupt from the PCI host bridge

(21071-CA)

Three jumpers (J3-3, J3-5, and J3-7) connect to one side of the multiplexer.

The jumper conﬁguration sets the CPU clock multiplier value through the

cpu_irqn inputs during reset.

Functional Elements 4–3