User`s manual

4
Functional Elements
This chapter describes some of the functional elements of the AlphaPC64.
Information, such as bus timing and protocol, found in other specifications,
data sheets, and reference documentation is not duplicated. Appendix B
provides a list of supporting documents and order numbers.
Note
For a detailed description of the Alpha 21064A, refer to the
Alpha 21064 and Alpha 21064A Microprocessors Hardware Reference
Manual.
For detailed descriptions of chipset logic, operations, and transactions,
refer to the DECchip 21071 and DECchip 21072 Core Logic Chipsets
Data Sheet.
For details of the PCI interface, refer to the PCI System Design Guide
and the PCI Local Bus Specification.
4.1 PCI Interrupts and Arbitration
The following subsections describe the PCI interrupt and arbitration (arbiter)
logic.
4.1.1 System Interrupts
Figure 4–1 shows the AlphaPC64 interrupt logic. Interrupt logic is
implemented in two programmable logic devices (PLDs), MACH210–20 and
22V10–25. The PLDs allow each PCI and PCI-to-ISA bridge chip interrupt to
be individually masked. The PLDs also allow the current state of the interrupt
lines to be read.
Functional Elements 4–1