User`s manual

1.2 System Components and Features
1.2.2 DECchip 21072 Support Chipset
The 21064A is supported by a DECchip 21072 ASIC chipset (21072), with a
128-bit memory interface. The chipset consists of the following three chips:
• DECchip 21071-CA (21071-CA) provides the interface from the CPU to
cache and main memory, and includes the cache and memory controller.
• DECchip 21071-BA (21071-BA) provides a 32-bit data path from the CPU
to memory and I/O. Four chips provide the 128-bit interface.
• DECchip 21071-DA (21071-DA) provides an interface from the CPU to the
peripheral component interconnect (PCI) bus.
The chipset includes the majority of functions required for a high-performance
PC or workstation, requiring minimum discrete logic on the motherboard. The
chipset provides flexible and generic functions to allow its use in a wide range
of systems.
For more information on the DECchip 21072 chipset, see the DECchip 21071
and DECchip 21072 Core Logic Chipsets Data Sheet.
1.2.3 PAL Control Set
The AlphaPC64 contains a 4-PAL control set and includes the following:
• Two 16V8-5 PALs provide L2 cache output-enable and write-enable
functions.
• One 22V10-25 PAL provides interrupt address decode functions and utility
bus (Ubus) control.
• One MACH210-20 PAL provides the PCI and ISA interrupts.
1.2.4 Level 2 Cache Subsystem Overview
The external level 2 (L2) cache subsystem supports 512KB, 2MB, or 8MB
cache sizes by using a 128-bit data bus. The L2 cache size can be reconfigured
through onboard hardware and software jumpers.
The AlphaPC64 supports the L2 cache SIMM sizes shown in Table 1–1. SIMM
types currently available and supported are 512KB @15 ns and 2MB @12 ns.
Two SIMMs are required per system. See Appendix A for ordering information.
1–4 AlphaPC64 Introduction