User`s manual

162
selected (if ANALOG input, output rate forced to 44.1kHz in
AutoSYNC position)
• Accommodates any valid S/PDIF digital input signal over a sample
rate range of 25-108kHz
Digital Processing
Digital Filters • 6144-tap flexible adaptive/fixed filter module, dynamically allocable
in 1024-tap sections to as many as 6 filter stages.
• Two 256-tap FIR filters for output equalizers.
• Four 256-tap FIR filters for input and output highpass filters.
• Four 128-tap FIR filters for interpolation / decimation.
• High-performance floating-point DSP processor that performs
broadband noise reduction functions and other advanced
algorithms
Limiter •· Microprocessor controlled
• Adjustable release time and threshold
AGC • Digital Implementation
• Adjustable release time and gain range
Control Microprocessor • TMS320C50 20 MIPS host processor with 32k x 16 program
RAM, 64k x 8 data EPROM, 64k x 8 boot EPROM, and 512k x 8
flash memory.
Slave Microprocessors • Two TMS320C50 20 MIPS processors with 32k x 16 program
RAM and 32k x 16 data (delay) RAM
• One TMS320C6713 1.8 GFLOPS floating-point processor with
1280MB data/program/delay RAM and 1MB Flash memory
Computers Interface • Standard RS232 serial interface for digital filter control, coefficient
transfer, and spectral analysis data. 9.6k to 115.2k baud transfer
rate, adjustable. (115.2k default)