Specifications

Control Block Description ADDvantage-32 PLUS
4-33
Regardless of the POS I LIMIT or NEG I LIMIT values for the motor current limits,
actual armature current cannot exceed 200% of the drive D.C. MAX CONT nameplate
current.
1. Inputs
POS I: Analog 0 - 300
NEG I: Analog 0 - 300
START PER: Analog 100 - 200
END PER: Analog 0 - 200
I2R TRIP: Analog 0 - 100
BY I2R: Bit
SFDBK: Analog
START PER S: Analog 0 - 200
END PER S: Analog 0 - 200
BRK SPD: Analog
MAX SPD: Analog
BLOCK POS: Bit
BLOCK NEG: Bit
2. Outputs
POS LIM: Analog 0 - 200
NEG LIM: Analog 0 - 200
3. Implementation
The Current Limit block emulates the block diagram in Figure 4-21.
The POS I LIMIT and NEG I LIMIT outputs are usually configured to the MAXL and
MINL inputs on the speed loop PI Control block.
Non-Tapered Current Limits
If non-tapered current limits are desired, the BY I2R input must be high by configuring
P***:BYPASS I2R = ONE BIT. The current limit block constantly monitors the I2R
Trip input (A***:IIR INTEGR) to detect when the motor armature current rises above
110%. The IIR INTEGR value will count up as long as the current is above 110%.
Should the armature current fall below 110%, the IIR INTEGR will count down. IF the
armature current stays above 110% long enough for IIR INTEGR to accumulate 100
counts, the drive will fault on a MOTOR (II) T fault.
The POS I LIMIT and NEG I LIMIT outputs will equal the POS I and NEG I input
values respectively.