Specifications
DigiPoS Retail Blade
™
Manual
Overview
x Host Interface
x System Memory Interface
x Hub Interface
x Communications Streaming Architecture (CSA) Interface
x Multiplexed AGP and Intel® DVO Interface
Host Interface
x Intel® Pentium® 4 processors with 512Kb L2 cache on 0.13 micron process /
Pentium 4 processor on 90 nm process
x 64-bit FSB frequencies of 400 MHz (100 MHz bus clock), 533 MHz (133 MHz
bus clock), and 800 MHz (200 MHz bus clock). Maximum theoretical BW of 6.4
GB/s.
x FSB Dynamic Bus Inversion on the data bus
x 32-bit addressing for access to 2 GB of memory space
x 12-deep In Order Queue
x AGTL+ On-die Termination (ODT)
x Hyper-Threading Technology
System Memory Controller
x Dual-channel (128 bits wide) DDR memory interface
x Single-channel (64 bits wide) DDR operation supported
x Symmetric and asymmetric memory dual-channel upgrade
x Non-ECC, un-buffered DIMMS only
x Up to 2 GB system memory
x Supports up to 16 simultaneously-open pages (four per row) in dual-channel
mode and up to 32 open pages in single-channel mode
x 4-KB to 64-KB page sizes (4 KB to 32 KB in single-channel, 8 KB to 64 KB in
dual-channel)
x Supports opportunistic refresh
x Suspend-to-RAM support using CKE
x SPD (Serial Presence Detect) Scheme for DIMM Detection supported
x Supports selective Command-Per-Clock (selective CPC) Accesses
x DDR (Double Data Rate type 1) Support
o Supports maximum of two DDR DIMMs single-sided and/or double-sided
o Supports DDR266, DDR333, DDR400 DIMM modules
o Supports DDR channel operation at 266 MHz, 333 MHz and 400 MHz
with a Peak BW of 2.1 GB/s, 2.7 GB/s, and 3.2GB/s respectively per
channel
o Burst length of 4 and 8 for single-channel (32 or 64 bytes per access,
respectively); for dual-channel a burst of 4 (64 bytes per access)
o Supports SSTL_2 signalling
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