Operating instructions

FRONT-PANEL DISTRIBUTION
The Front-Panel Distribution diagram shows the intercon-
nections between front-panel functions (controls, connect-
ors,
and indicators) and circuit boards within this
instrument .
The Trigger Generator provides a stable display
by starting
the Sweep Generator (diagram 4) at a selected point
on the
input waveform . The triggering point can be varied
by the
LEVEL control and may be on either the positive
or nega-
tive slope of the waveform . The triggering signal
source
may be from either the signal being displayed (INT), a
sig-
nal from an external source (EXT), or a sample of
the
power-line voltage (LINE) . A block diagram of
the Trigger
Generator is shown in Figure 3-2 .
External Source
TRIGGER GENERATOR
The external trigger signal
is connected to the Trigger Gen-
erator
through EXT TRIG IN connector J12 . Push-button
switch S10 provides 10 times attenuation of the external
trigger input signal .
When SOURCE switch (S50) is set to EXT, external signals
below approximately 16 kilohertz are coupled through R 15
and R20 to External Trigger Amplifier Q22 . Ac coupling is
provided by C15 . Triggering signals above 16
kilohertz are
coupled through C20 to the gate of Q22A
.
Field-effect transistors Q22A
and Q22B form a unity-gain
source follower, which couples
the external trigger signal to
the Trigger Source Selector and
Amplifier
stage
(U65-pin 4) .
Diodes CR23 and CR24 provide
input protection by clamp-
ing the input within a diode drop
of ground (approximately
0 .7 volt) .
Internal and Line Source
The internal trigger signal from the vertical
channel of the
mainframe is connected to the Internal
Trigger Amplifier
stage (U35) differentially via interface
connector pins A20
and B20 .
Internal trigger
signals with frequencies above 16 kilohertz
are coupled
through C37 directly into the Trigger Source
Selector and Amplifier stage (U65-pin 8) . Internal trigger
signals with frequencies below 16 kilohertz are coupled
dif-
ferentially through R31 and R33 to U35-pins
2 and 3 . The
single-ended output at U35-pin 6 is
coupled, along with the
offset from
LEVEL
control R60, to
U65-pin 10 . Ac coupl-
ing is provided by
C43 .
Theory of Operation-71380
A sample
of
the line voltage is connected to the trigger cir-
cuits
via interface connector pin A4 . The line signal is
connected to the Trigger Source Selector and Amplifier
stage
at U65-pin 2 .
Trigger Source Selector and Amplifier
The Trigger Source Selector and
Amplifier stage (partial
U65) determines whether the triggering
signal source is
from the signal being displayed
(INT), a signal from an ex-
ternal source (EXT), or a sample of
the power line voltage
(LINE) .
The trigger source is selected by
SOURCE switch S50 by
connecting the most positive voltage
to the source input of
U65 (refer to Figure 3-3) .
The voltage offset from LEVEL
control R60 is coupled to U65-pin 10 .
The differential trig-
ger output signal from U65-pins 16
and 17 is coupled to the
Slope Selector and Trigger Generator
stage (U85) .
High-frequency
reject coupling is provided in the Trigger
Source Selector
stage
. When the ACHF REJ push button is
pressed, C68 and components internal to U65-pin
9 form a
high-frequency rejection filter . Only
low-frequency ac trig-
gering signals are accepted
.
Peak-to-Peak Auto
The Peak-to-Peak Auto function can be divided into
3 dis-
tinct blocks . First, the Peak Detector
determines signal size
and do positioning . Second, a
DC Centering loop centers
the peak-detected output
regardless of the do input and off-
set voltages . Third,
the Peak-to-Peak Level Range output
voltage is
automatically adjusted until the trigger output
reaches the clamp
level set
by the
Automatic Gain Control
to achieve full level range
(refer
to
the Specification section
in this manual for level
range parameters) .
PEAK
DETECTOR . The peak detector outputs from U65-
pins 14 and 15,
rectified within U65, are externally filtered
by C73 and C74 . Secondary
stages of peak detection for
the positive and negative
detector signals are provided by
U75A-CR71-C72
and U75B-CR75-C76 . Outputs from the
Peak Detector stage
are coupled to the Peak-to-Peak Level
Range and DC Centering stages .
DC CENTERING . Operational amplifier U55B
adjusts the
input level at U65-pin 10 to null the do
input voltage and
accumulated do offsets . This
allows the trigger outputs at
U65-pins 16 and 17 to balance
when LEVEL control R60 is
set to zero . DC
Balance adjustment R85 provides centering
for offset voltages due to circuitry external to U65-pins 16
and 17 (e .g ., U85) .
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