Data Sheet
2/10/2018 Zybo Z7 Reference Manual [Reference.Digilentinc]
https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual 30/33
The MIPI CSI-2 bus is passively terminated on the Zybo Z7 and connected directly to the Zynq PL. The guidelines described in Xilinx
application note XAPP894 D-PHY solutions (https://www.xilinx.com/support/documentation/application_notes/xapp894-d-phy-solutions.pdf)
were followed in order to implement a compatible D-PHY receiver using the Zynq. The interface is tested to operate at up to 672 Mbps on
each lane. Speeds up to 950 Mbps on each lane are possible based on the Zynq-7000 timing specifications, however they are not validated
on the Zybo Z7.
A MIPI CSI-2 Receiver IP core (https://www.xilinx.com/products/intellectual-property/ef-di-mipi-csi-rx.html) is available from Xilinx, and
includes embedded Linux support. It requires a license in order to use, however it is possible to obtain an evaluation license from Xilinx for
free.
A reference implementation with a basic feature set of both D-PHY and CSI-2 will be provided by Digilent in our Github repository.
Pmod ports are 2×6, right-angle, 100-mil spaced female connectors that mate with standard 2×6 pin headers. Each 12-pin Pmod port
provides two 3.3V VCC () signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure 16.1. The
VCC () and Ground pins can deliver up to 1A of current, but care must be taken not to exceed any of the power budgets of the on-board
regulators or the external power supply (these are described in the “Power supplies” section).
(https://reference.digilentinc.com/_detail/basys3-pmod_connector.png?id=reference%3Aprogrammable-logic%3Azybo-z7%3Areference-manual) Figure
16.1. Pmod port
Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod ports to add ready-made functions like A/D’s,
D/A’s, motor drivers, sensors, and other functions. See www.digilentinc.com (http://www.digilentinc.com) for more information. The
vivado-library repository on the Digilent Github (https://github.com/Digilent/) contains pre-made IP cores for many of these Pmods that
greatly reduces the work of integrating them into your project. See the “Using Pmod IP” tutorial on the Zybo Z7 Resource Center for help
using them.
The Zybo Z7 has six Pmod ports, some of which behave differently than others. Each Pmod port falls into one of four categories: standard,
MIO connected, XADC, or high-speed. Table 16.1 specifies which category each Pmod port falls into, and also lists the Zynq pins they are
connected to. The sections that follow describe the different types of Pmods.
Pmod JA Pmod JB* Pmod JC Pmod JD Pmod JE Pmod JF
Pmod Type XADC High-Speed High-Speed High-Speed Standard MIO
Pin 1 N15 V8 V15 T14 V12 MIO-13
Pin 2 L14 W8 W15 T15 W16 MIO-10
Pin 3 K16 U7 T11 P14 J15 MIO-11
Pin 4 K14 V7 T10 R14 H15 MIO-12
Pin 7 N16 Y7 W14 U14 V13 MIO-0
Pin 8 L15 Y6 Y14 U15 U17 MIO-9
Pin 9 J16 V6 T12 V17 T17 MIO-14
Pin 10 J14 W6 U12 V18 Y17 MIO-15
*Pmod JB is not available on the Zybo Z7-10
16 Pmod Ports
