EDK Base System Builder (BSB) support for XUPV2P Board Xilinx University Program May 2005
What is BSB? • The Base System Builder (BSB) wizard is a software tool that help users quickly • • • • build a working system targeted at a specific development board. Based on the user’s board selection, BSB will offer the user a number of options for creating a basic system on that board. These options include processor type, debug interface, cache configuration, memory type and size, and peripheral selection. For each option, functional default values will be preselected in the GUI.
Objective • Use a BSB design (or derivative) as the basis for: – Standalone processor based designs – Board Support Packages for PP405 Linux and Microblaze uCLinux • Since it is a general tool, BSB designs are not optimum for every configuration but provide a starting point for further development since it provides reasonable defaults for all parameters not changed by the user XUPV2P BSB support 3 May 2005
XUPV2P Development System XUPV2P BSB support 4 May 2005
Mini-Howto • Use EDK 7.1 SP1 (H.11.3) and ISE 7.1 SP2 (H.
BSB Board Selection • Select “I would like to create a new design” versus using a previous BSB session as a starting point • The “XUP Virtex-II Pro Development System” should be listed under the Xilinx board vendor XUPV2P BSB support 6 May 2005
BSB Processor Selection • BSB supports both the PowerPC405 and Microblaze processors, select the Microblaze processor for now XUPV2P BSB support 7 May 2005
BSB Processor Options • Accept the default Microblaze Processor Options XUPV2P BSB support 8 May 2005
BSB Peripheral Selection • The user can now include various peripherals provided on the board and select among parameters for each peripheral – Select to include RS232_UART_1, LEDs_4Bit, DIPSWs_4Bit, and PushButtons_5Bit • BSB will optionally create example software applications (TestApps) – Accept default options XUPV2P BSB support 9 May 2005
BSB System Overview • Finally BSB lists the system configuration summary for the generated design XUPV2P BSB support 10 May 2005
EDK Xilinx Platform Studio (XPS) • After BSB finishes, XPS provides several options for the next path ! Select Download the design – Any of these operations can be performed from the main XPS window – However, before the design can be downloaded, it must first be implemented XUPV2P BSB support 11 May 2005
Design Implementation • A bunch of things happen under the hood!! – An HDL representation of the design will be created in the hdl directory – Each submodule is synthesized into netlists stored in subdirectories under – – – – – – implementation Ngdbuild combines the netlists and performs DRCs The netlist is placed and routed (par) and a bitfile is generated The software device drivers are compiled into libraries The user application is compiled and linked against the libraries to created an executable elf
Serial Output • Connect a RS232 serial cable from the XUP-V2P board serial port to the PC • Open a terminal (i.e.
You’ve Done It! You have just implemented a System-on-Chip Design using a Xilinx FPGA! XUPV2P BSB support 14 May 2005
TestApplication • BSB also generates a simple test application – Each IO EDK peripheral is wiggled by software – LEDs are flashed and the Switches/Pushbuttons are read • First, enable the TestApp_Peripheral • Then, uncomment the xil_printfs so that the state of the switches/pushbuttons are displayed XUPV2P BSB support 15 May 2005
Interfacing with Peripherals 1) Disable “Mark to Initialize BRAMs” 1) Enable “Mark to Initialize BRAMs” XUPV2P BSB support 16 May 2005
TestApplication Modification Uncomment to print values Uncomment to print values XUPV2P BSB support 17 May 2005
Downloading the TestApp • Select Tools!Download and the software is recompiled, programmed into the FPGA bitstream, and then downloaded to the board The FPGA was configured twice. The second time the two left DipSwitches were moved to the up position resulting in different values being read.
Simulation Setup • Select Options!Project Options and either point to already compiled libraries or compile them new – Note: For PowerPC405 simulations, also need to set up SmartModel SWIFT support.
Simulation Script • Select Tools!Start HDL Simulator – Enter the following commands (or as a do script) at the modelsim prompt – Note: Do not have external peripherals modeled XUPV2P BSB support 20 May 2005
Modelsim Simulation Commands # Make sure to set EDK to compile for verilog do system.do vsim system system_conf glbl add wave -radix hexadecimal /* # Enable the viewing of the Microblaze registers ... set mb_register_path "/system/microblaze_0/microblaze_0/data_flow_i" # ...
Waveform Output “Ente” being sent to the JTAG UART (part of the actual data transmission) XUPV2P BSB support 22 May 2005
Design Size and Implementation Time • Design Size: Currently only 3% of 2VP30 FPGA for entire Microblaze design – There is a lot of room for more peripherals! • Implementation Time from start to finish: Half Hour! XUPV2P BSB support 23 May 2005
