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Digilent Parallel Interface Model Digilent, Inc.

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Port (

mclk : in std_logic;

pdb : inout std_logic_vector(7 downto 0);

astb : in std_logic;

dstb : in std_logic;

pwr : in std_logic;

pwait : out std_logic;

rgLed : out std_logic_vector(7 downto 0);

rgSwt : in std_logic_vector(7 downto 0);

rgBtn : in std_logic_vector(4 downto 0);

btn : in std_logic;

ldg : out std_logic;

led : out std_logic

);

end dpimref;

architecture Behavioral of dpimref is

------------------------------------------------------------------------

-- Component Declarations

------------------------------------------------------------------------

-- Local Type Declarations

------------------------------------------------------------------------

-- Constant Declarations

------------------------------------------------------------------------

-- The following constants define state codes for the EPP port interface

-- state machine. The high order bits of the state number give a unique

-- state identifier. The low order bits are the state machine outputs for

-- that state. This type of state machine implementation uses no

-- combination logic to generate outputs which should produce glitch

-- free outputs.

constant stEppReady : std_logic_vector(7 downto 0) := "0000" & "0000";

constant stEppAwrA : std_logic_vector(7 downto 0) := "0001" & "0100";

constant stEppAwrB : std_logic_vector(7 downto 0) := "0010" & "0001";

constant stEppArdA : std_logic_vector(7 downto 0) := "0011" & "0010";

constant stEppArdB : std_logic_vector(7 downto 0) := "0100" & "0011";

constant stEppDwrA : std_logic_vector(7 downto 0) := "0101" & "1000";

constant stEppDwrB : std_logic_vector(7 downto 0) := "0110" & "0001";

constant stEppDrdA : std_logic_vector(7 downto 0) := "0111" & "0010";

constant stEppDrdB : std_logic_vector(7 downto 0) := "1000" & "0011";

------------------------------------------------------------------------

-- Signal Declarations

------------------------------------------------------------------------

-- State machine current state register

signal stEppCur : std_logic_vector(7 downto 0) := stEppReady;

signal stEppNext : std_logic_vector(7 downto 0);

signal clkMain : std_logic;

-- Internal control signales

signal ctlEppWait : std_logic;