Data Sheet

Nexys Video™ FPGA Board Reference Manual
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Page 26 of 29
15 OLED
A Univision Technology Inc. UG-2832HSWEG04 is loaded on the Nexys Video. It is a white monochrome, 128 x 32, 0.91" organic LED display
0.91" organic LED display matrix bundled with a Solomon Systech SSD1306 display controller. The display data interface towards the FPGA is a 4-
interface towards the FPGA is a 4-wire serial peripheral interface (SPI). The 4 wires in controller-terminology are CS#, D/C#, SDIN, and SCLK, but
CS#, D/C#, SDIN, and SCLK, but CS# is hard-wired to ground. This adds to the reset and two power control signals for proper start-up sequencing.
for proper start-up sequencing. The signals are summarized in
Table 11.
Signal
Description
Polarity
FPGA pin
RES#
Reset
Active-low
U21
CS#
Chip select (always active)
Active-low
N/A
D/C#
Data (high)/Command (low)
Both
W22
SCLK
Serial Clock
Active-high
W21
SDIN
Serial Data
Active-high
Y22
VBAT#
Power enable for internal power supply
Active-low
P20
VDD#
Power enable for digital power
Active-low
V22
Table 112. OLED signal description.
The serial interface is synchronous to SCLK and must conform to the timing specifications below. In most cases, a
10 MHz SCLK and data sent on the falling edge should work.
Figure 15. Serial interface timing diagram.
Figure 17. OLED serial interface bit ordering.