Data Sheet

Nexys Video™ FPGA Board Reference Manual
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Page 23 of 29
CEC
Consumer Electronics Control
bidirectional
AA4
Consumer Electronics Control
bidirectional
AA5
SCL, SDA
DDC bidirectional
U3, V3
DDC bidirectional
Y4, AB5
HPD/HPA
Hot-plug detect input
AB13
Hot-plug assert output
AB12
5V0
Powered from 5V rail
N/A
Powers auxiliary signals
N/A
TXEN
Transmitter enable output
R3
Table 11. HDMI pin description and assignment.
13.1 TMDS signals
HDMI/DVI is a high-speed digital video stream interface using transition-minimized differential signaling (TMDS).
To make proper use of either of the HDMI ports, a standard-compliant transmitter or receiver needs to be
implemented in the FPGA. The implementation details are outside the scope of this manual. Check out the Nexys
Video Resource Center for ready-to-use reference IP.
13.2 Auxiliary signals
A pull-down resistor on the TXEN signal makes sure the sink buffer's transmitter facing the FPGA is disabled by
default. An FPGA design using the sink port needs to actively drive this pin high for the buffer to pass data through.
Whenever a sink is ready and wishes to announce its presence, it connects the 5V0 supply pin to the HPD pin. On
the Nexys Video, this is done by driving the Hot Plug Assert signal high. Note: this should only be done after a DDC
channel slave has been implemented in the FPGA and is ready to transmit display data.
The Display Data Channel, or DDC, is a collection of protocols that enable communication between the display
(sink) and graphics adapter (source). The DDC2B variant is based on I
2
C, the bus master being the source and the
bus slave the sink. When a source detects high level on the HPD pin, it queries the sink over the DDC bus for video
capabilities. It determines whether the sink is DVI or HDMI-capable and what resolutions are supported. Only
afterwards will video transmission begin. Refer to VESA E-DDC specifications for more information.
The Consumer Electronics Control, or CEC, is an optional protocol that allows control messages to be passed
around on an HDMI chain between different products. A common use case is a TV passing control messages
originating from a universal remote to a DVR or satellite receiver. It is a one-wire protocol at 3.3V level connected
to an FPGA user I/O pin. The wire can be controlled in an open-drain fashion allowing for multiple devices sharing a
common CEC wire. Refer to the CEC addendum of HDMI 1.3 or later specifications for more information.
14 DisplayPort Output
DisplayPort is a relatively new industry standard for digital display technology. The advantages of DisplayPort over
existing technologies are: higher bandwidth for greater resolutions and color depths, bi-directional auxiliary
channel, variable interface width, and flexible power topologies, among others.
DisplayPort defines a high-speed main link carrying audio and video data, an auxiliary channel, and a hot-plug
detect signal. The main link is a unidirectional, high-bandwidth and low-latency channel. It consists of one, two, or
four AC-coupled differential pairs, called lanes. Version 1.1 of the standard defines two link rates: 1.62 and 2.7
Gbps. The lanes carry both data and an embedded clock at the link rate negotiated between Source and Sink,
independent of the resolution and color depth of the video stream. The link rate is de-coupled from the pixel rate,