Data Sheet

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Nexys Video™ FPGA Board Reference Manual

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Artix-7

FT2232H

JTAG

Micro-USB

(J12)

U20D0/SCK

P14D1/MOSI

P15D2/MISO

U17D3/SS

Y19TXE#

N17RXF#

N14D7

R18D6

P16D5

R17D4

P19RD#

R19WR#

P17SIWU#

V17OE#

Y18CLKOUT

Figure 6. USB-FPGA interfaces provided by the USB PROG port.

7.1 Parallel Transfer Interface (DPTI)

DPTI is an 8-bit wide parallel FIFO-style data interface that offers higher bandwidth than DSPI. In FTDI-terminology,

DPTI is equivalent to "FT245-style Asynchronous or Synchronous FIFO Interface". It is available in both synchronous

and asynchronous modes, configurable from the DPTI API. In synchronous mode, data transfer is timed by the

clock provided by the USB controller that is input to the FPGA. In asynchronous mode, data transfer is happening

on transitions of read and write control signals. The USB controller emulates a FIFO memory, providing status

signals about the availability of data to be read or free space for data to be written. The FPGA controls data

transfer by read, write, and output enable signals.

Signal

Direction (FPGA

Point of View)

Description

D[7:0]

I/O

Data bus.

RXF#

Input

When low, data is available for reading from the FIFO.

TXE#

Input

When low, data can be written to the FIFO.

RD#

Output

A low-pulse triggers data to be read out from the FIFO.

WR#

Output

A low-pulse triggers data to be written to the FIFO.

SIWU#

Input

Send immediate or Wake-up function. In normal mode a low pulse triggers

sending a data packet with the data currently in the FIFO, even if below the

normal packet size. In suspend mode a low pulse can wake up the Host PC.

OE#

Output

When low, the data bus is driven by the USB controller (read transfer). When

high, the bus is driven by the FPGA (write transfer).

CLKO

Input

60 MHz clock used in synchronous mode. Data is launched and can be

captured on the rising edge.

Table 5. DPTI signal description.

For more information, see the FT2232H data sheet.