User Manual

Digilent
FX12 Reference Manual
www.digilentinc.com
Copyright Digilent, Inc. Page 4/18 Doc: 502-046
Supply
Max
Current
Regulator
Part
Number
Devices Powered Notes
3.3V 4A LTC3416
• Hirose expansion connector
• Xilinx FPGA I/O banks 2, 4, 6, 7,
and 8
• Micron Flash memory
• RS-232 level shifter
• Analog Devices Video DAC
• ICS frequency synthesizer
Uses oversized 3.3uH
inductor for stability at
low current.
2.5V 4A LTC3416
• Xilinx Platform Flash
• Xilinx FPGA I/O banks 1, 3, 5, 7,
and 8
• ISSI DDR DRAM’s
• Marvell 88E1111 Ethernet PHY
Uses oversized 3.3uH
inductor for stability at
low current.
1.8V 150mA LTC1844
• Xilinx Platform Flash
1.25V 2A LTC3413
• DDR termination networks
Uses oversized 1.5uH
inductor for stability at
low current.
1.2V 8A LTC3418
• Xilinx FPGA core
• Marvell PHY core
Oscillator
The FX12 includes a 350MHz, crystal-to-
LVCMOS frequency synthesizer from
Integrated Circuit Systems Inc (PN
ICS8402). The synthesizer gets its primary
frequency input from a 25MHz crystal, and
then multiplies that input up to the desired
output frequency. The output frequency is
selected by the DIP switches at SW1,
according to the table in Appendix A. The
clock output from the synthesizer is
delivered to the FPGA on the GCLK0 input
at pin Y5.
A secondary input is also available to drive
a different base frequency into the
synthesizer. The socket labeled “test_clk”
can accommodate any 12-40MHz LVCMOS
oscillator in a half-DIP package. This
secondary source will drive the synthesizer
if the XTAL_SEL signal is driven high from
the FPGA. The oscillator circuit is shown in
the accompanying figure. Please see the
ICS8402 data sheet for further information.
Frequency
Synthesizer
Frequency Select
Switches
SMA Cloc k
Inputs to FPGA
Secondary
Clock Input
Primary Crystal
(25MHz)
SMA Clock
Output
Clock Source
Select Jumper
FX12 Oscillator Circuit