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DIO5 Reference Manual Digilent, Inc.

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rgbSwt : in std_logic_vector(7 downto 0);

encBtn : out std_logic_vector(3 downto 0);

rgbBtnOt : out std_logic_vector(5 downto 0);

rgbLed : out std_logic_vector(15 downto 0);

rgbSsgAn : out std_logic_vector(3 downto 0);

rgbSsgCa : out std_logic_vector(7 downto 0);

kclk : out std_logic;

kdat : out std_logic;

kcin : in std_logic;

kdin : in std_logic);

end DlabDio5;

architecture Behavioral of DlabDio5 is

------------------------------------------------------------------------

-- Component Declarations

------------------------------------------------------------------------

-- Constant and Signal Declarations

------------------------------------------------------------------------

-- Internal registers for output devices

signal regLed : std_logic_vector(15 downto 0);

signal regSsg : std_logic_vector(15 downto 0);

signal regBtn : std_logic_vector(15 downto 0);

signal rgbSyncBtn : std_logic_vector(15 downto 0);

-- Other needed signals

signal busDout : std_logic_vector(7 downto 0);

signal cntDig : std_logic_vector(1 downto 0) := "00";

signal ssg : std_logic_vector(6 downto 0);

signal dig : std_logic_vector(3 downto 0);

signal an : std_logic_vector(3 downto 0);

----------------------------------------------------------------------------

-- Module Implementation

----------------------------------------------------------------------------

begin

------------------------------------------------------------------------

-- Bus drive control logic. Data bus is driven only when oe and cs are valid.

------------------------------------------------------------------------

db <= busDout when (oe = '0' and cs = '0') else "ZZZZZZZZ";

-- Output mux to place selected data on bus

busDout <= rgbSyncBtn(7 downto 0) when adr = "000000" else

rgbSyncBtn(15 downto 8) when adr = "000001" else

rgbSwt when adr = "000010" else

rgbLcd;

------------------------------------------------------------------------

-- Registers for On-Board Output Devices (LEDs and Sseg display)

------------------------------------------------------------------------

-- The WE signal is driven from a global clock buffer.

process (we)

begin

if (we'event and we = '1') then

if (adr = "000000" and cs = '0') then regLed( 7 downto 0) <= db; end if;

if (adr = "000001" and cs = '0') then regLed(15 downto 8) <= db; end if;

if (adr = "000010" and cs = '0') then regSsg( 7 downto 0) <= db; end if;