Manual

Opus Card – DDR-2 Interface
Reference Manual
12/03/2010 07:35 AM 22
Copyright © 2009-2010 by CML
3.3.7 Burst Memory Read - Four 64-bit Words
The timing diagram below is for a four 64-bit word burst read. Data is buffered to a FIFO as it is
read from the DDR-2 controller. The data is then read from the FIFO as it is transferred to the
PLB slave.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Read
Add r+4
Wor d 12 Wor d 34
Word1
Address
Idle
Queue_ D1
IdleWait_ RdVal i d
Queue _D2 FIFO_Read
Signals below are from write_ctrl
0x20
Word2 Wo rd3 Word 4
0x0 0x2 0x0
FIFO_Rd Lo_Bits Lo_Bits
Idle Idle
Read
Addr
0x1 0x2
Wor d 56 Wor d 78
Queue _D1 Queue_D2
0x1
Lo_Bi ts Lo_Bi ts
Address + 0x08 Address + 0x10 Address + 0x18
FIFO_Rd FIFO_Rd FIFO_Rd
TimeGen
DDR2_Clk
Bus2IP_Clk
Bus2IP_CS
Bus2IP_Burst
Bus2IP_BurstLength
Bus2IP_RNW
Bus2IP_Addr
Bus2IP_RdReq
IP2Bus_Data
Rd_Send_Cmd
burst_ack
Rd_Send_Ack
Rd_Data_Valid
Rd_Data_FIFO_Out
Rd_Burst_Cnt
rdfifo_empty
rdfifo_rden
State
FIFO_State
IP2Bus_AddrAck
IP2Bus_RdAck
App_AF_WREn
App_AF_Cmd
App_AF_Addr