Manual

Opus Card – DDR-2 Interface
Reference Manual
12/03/2010 07:35 AM 20
Copyright © 2009-2010 by CML
3.3.5 Burst Memory Read - Eight 32-bit Words
The timing diagram below is for an eight 32-bit word burst read. Data is buffered to a FIFO as it
is read from the DDR-2 controller. The data is then read from the FIFO as it is transferred to the
PLB slave.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Read
Add r+4
Word 12 Word 34
Word1
Address
Idle
Q_D1
IdleWai t_ RdV al i d
Queu e _D2 FIFO_Read
Signals below are from write_ctrl
0x20
Word2 Word3 Wo rd 4
Add ress + 0x0 4
0x0 0x2 0x0
F_Rd F_RdHi_Bits Lo_Bits Lo_BitsHi_Bits
Idle Idle
Ad d ress + 0x0 8 Ad dre ss + 0 x0 C
Read
Add r
0x1 0x2
Word 56 Word 78
Q_D 1 Q_D2
0x1
Word5 Word6 Word7 Word8
Ad d ress + 0x1 0 Ad d re ss + 0 x1 4 Ad d re ss + 0x18 Ad dre ss + 0 x1C
F_Rd F_RdHi_Bits Hi_BitsLo_Bits Lo_Bits
TimeGen
DDR2_Clk
Bus2IP_Clk
Bus2IP_CS
Bus2IP_Burst
Bus2IP_BurstLength
Bus2IP_RNW
Bus2IP_Addr
Bus2IP_RdReq
IP2Bus_Data
Rd_Send_Cmd
burst_ack
Rd_Send_Ack
Rd_Data_Valid
Rd_Data_FIFO_Out
Rd_Burst_Cnt
rdfifo_empty
rdfifo_rden
State
FIFO_State
IP2Bus_AddrAck
IP2Bus_RdAck
App_AF_WREn
App_AF_Cmd
App_AF_Addr