Manual

Opus Card – DDR-2 Interface
Reference Manual
12/03/2010 07:35 AM 12
Copyright © 2009-2010 by CML
2.3.6 Burst Memory Write - Four 64-bit Words
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Wri te
Address+ 4
Word 3 Wo rd 4
0x0
Word 1
Address
Byte Enables (All 1's for a burst)
Idle Wait_WrReq
Wr_Brst1
Wr_Br st2
Word 2 Word 3 Word 4
Address+0x8 Address+0x10 Address+0x18
IdleSave_W1
Wri te
Address
Word 1 Wo rd 2
0x0
Wr_Brst1 Wr_Brst2
Save_W1
Wr_Br stD Wr_Br stD
TimeGen
DDR2_Clk
Bus2IP_Clk
Bus2IP_CS
Bus2IP_Burst
Bus2IP_RNW
Bus2IP_Addr
Bus2IP_BE
Bus2IP_WrReq
Bus2IP_Data
IP2Bus_AddrAck
IP2Bus_WrAck
App_AF_WREn
App_AF_Cmd
App_AF_Addr
App_WDF_WREn
App_WDF_Data
App_WDF_Mask_Data
State