Manual

Opus Card – DDR-2 Interface
Reference Manual
12/03/2010 07:35 AM 11
Copyright © 2009-2010 by CML
2.3.5 Burst Memory Write – Two 64-bit Words
1 2 3 4 5 6 7 8 9 10 11 12 13
Wri te
Address
Word 1 Word 2
0x0
Word 1
Address
Byte Enables (All 1's for a burst)
Idle Wait_WrReq
Wr_Burst1
Wr_Burst2
Word 2
Address+0x8
Save_W1
Idle
Wr_BurstD
TimeGen
DDR2_Clk
Bus2IP_Clk
Bus2IP_CS
Bus2IP_Burst
Bus2IP_RNW
Bus2IP_Addr
Bus2IP_BE
Bus2IP_WrReq
Bus2IP_Data
IP2Bus _AddrAck
IP2Bus _WrAck
App_AF_WREn
App_AF_Cmd
App_AF_Addr
App_WDF_WREn
App_WDF_Data
App_WDF_Mask_Data
State