User guide
Atlys Reference Manual
Doc: 502-178 page 11 of 19
and one reserved (RES) pin. Of these, only the differential data channels and I2C bus are connected
to the FPGA. All signal connections are shown in the table below.
HDMI Type A Connectors
HDMI Type D
Pin/Signal
J1: IN
J2: Out
J3: IN
Pin/Signal
JA: BiDi
1:
D2+ B12 B8 J16 1:
HPD
JP3
*
2:
D2_S
GND
GND
GND
2:
RES
VCCB2
3:
D2- A12 A8 J18 3:
D2+ N5
4:
D1+ B11 C7 L17 4:
D2_S
GND
5:
D1_S
GND
GND
GND
5:
D2- P6
6:
D1- A11 A7 L18 6:
D1+ T4
7:
D0+ G9 D8 K17 7:
D1_S
GND
8:
D0_S
GND
GND
GND
8:
D1- V4
9:
D0- F9 C8 K18 9:
D0+ R3
10:
Clk+ D11 B6 H17 10:
D0_S
GND
11:
Clk_S
GND
GND
GND
11:
D0- T3
12:
Clk- C11 A6 H18 12:
Clk+ T9
13:
CEC
NC
0K to Gnd
NC
13:
Clk_S
GND
14:
RES
NC
NC
NC
14:
Clk- V9
15:
SCL C13 D9 M16 15:
CEC
VCCB2
16:
SDA A13 C9 M18 16:
Gnd
GND
17:
Gnd
GND
GND
GND
17:
SCL C13**
18:
5V
JP4*
5V
JP8
* 18:
SCA A13**
19:
HPD
1K to 5V
NC
1K to 5V
19:
5V
JP3
*jumper can disconnect Vdd **shared with J1 I2C signals via jumper JP2