Data Sheet

3/8/2018 Arty Z7 Reference Manual [Reference.Digilentinc]
https://reference.digilentinc.com/reference/programmable-logic/arty-z7/reference-manual 22/24
(https://reference.digilentinc.com/_media/reference/programmable-logic/arty-z7/arty-z7-shield-an.png)
Figure 16.2.1. Single-Ended Analog Inputs.
The pins labeled A6-A11 are connected directly to 3 pairs of analog capable pins on the Zynq PL via an anti-aliasing filter. This circuit is
shown in Figure 16.2.2. These pairs of pins can be used as differential analog inputs with a voltage difference between 0-1V. The even
numbers are connected to the positive pins of the pair and the odd numbers are connected to the negative pins (so A6 and A7 form an
analog input pair with A6 being positive and A7 being negative). Note that though the pads for the capacitor are present, they are not loaded
for these pins. Since the analog capable pins of the FPGA can also be used like normal digital FPGA pins, it is also possible to use these
pins for Digital I/O.
The pins labeled V_P and V_N are connected to the VP_0 and VN_0 dedicated analog inputs of the FPGA. This pair of pins can also be
used as a differential analog input with voltage between 0-1V, but they cannot be used as Digital I/O. The capacitor in the circuit shown in
Figure 16.2.2 for this pair of pins is loaded on the Arty Z7.
(https://reference.digilentinc.com/_media/reference/programmable-logic/arty-z7/arty-z7-shield-diff-an.png)
Figure 16.2.2. Differential Analog Inputs.
The XADC core within the Zynq is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be
driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via the
Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power
rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document
titled “7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter”. It is also possible
to access the XADC core directly using the PS, via the “PS-XADC” interface. This interface is described in full in chapter 30 of the Zynq
Technical Reference manual (http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf).
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