300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com NetFPGA-1G-CML™ Board Reference Manual Revised July 16, 2014 This manual applies to the NetFPGA-1G-CML rev. E Table of Contents Table of Contents .................................................................................................................. 1 Overview............................................................................................................................... 3 1 FPGA Configuration ..................
NetFPGA-1G-CML™ Board Reference Manual 14 FMC Expansion Connector ............................................................................................ 11 Appendix A: Manufacturing Test.......................................................................................... 12 Appendix B: FPGA Pin Constraints........................................................................................ 13 System Clock and Reset ..............................................................................
NetFPGA-1G-CML™ Board Reference Manual Overview The NetFPGA-1G-CML is a versatile, low cost network hardware development platform featuring a Xilinx® Kintex®7 XC7K325T FPGA and includes four Ethernet interfaces capable of negotiating up to 1 GB/s connections. 512 MB of 800 MHz DDR3 can support high-throughput packet buffering while 4.5 MB of QDRII+ can maintain low-latency access to high demand data, like routing tables.
NetFPGA-1G-CML™ Board Reference Manual The Kintex-7 XC7K325T-1FFG676 FPGA has ample logic and I/O capacity for supporting a wide range of designs with the following capabilities: • • • • • • • • 1 50,950 slices, each containing four 6-input LUTs and eight flipflops Over 16 Mbit of fast on-chip block RAM Ten clock management tiles with one PLL and one mixed-mode clock manager each 840 DSP slices Integrated PCI Express Integrated AES bitstream encryption and SHA-256 authentication with batterybacked encry
NetFPGA-1G-CML™ Board Reference Manual programs the FPGA directly with a special purpose BPI flash interface. It will then transfer the .mcs bitstream to the flash through that interface. This process is fully automated by the iMPACT program, so a designer only needs to be concerned with the creation of the .mcs file using Xilinx’s design software.
NetFPGA-1G-CML™ Board Reference Manual The Xilinx Kintex-7 Data Sheet: DC and AC Switching Characteristics (DS182) provides more information on the power supply requirements of the FPGA board. Supply Derived From Application 5.0 V 12.0 V 3.3 V 12.0 V 2.0 V 5.0 V 1.8 V 1.8 V 1.5 V 1.2 V 1.0 V 1.0 V 0.9 V 0.75 V 12.0 V 3.3 V 12.0 V 12.0 V 12.0 V 3.3 V 3.3 V 3.
NetFPGA-1G-CML™ Board Reference Manual 4 FPGA Memory The XC7K325T FPGA includes 445 on-chip Block RAMs (BRAMs) of 36Kb, or 4096 bytes with two-bit error correction, which amounts to a total of 1.78 MB of on-chip, error-corrected static RAM that can be used for a variety of purposes ranging from program storage for deeply embedded “bare metal” applications to data buffering and table lookup.
NetFPGA-1G-CML™ Board Reference Manual The BPI flash has enough capacity to store multiple device configurations. This facilitates multi-stage configuration boot as well as applications that utilize dynamic reconfiguration. Configuration bitstreams are not the only data which can be stored in the BPI flash. After configuration is complete, the BPI programming pins may be used as normal Select I/O within the design.
NetFPGA-1G-CML™ Board Reference Manual Data is transferred to and from the PHYs via a Reduced Gigabit Media Independent Interface (RGMII). This is similar to the Gigabit Media Independent Interface (GMII), which uses eight bits for both transmit and receive data. RGMII achieves the same data rate with half the number of data bits and double-data-rate clocking. 1 Gbps data transfers are thereby achieved using a 125MHz clock with four bits transferred on each clock edge for both send and receive.
NetFPGA-1G-CML™ Board Reference Manual Component Name PIC I2C Controller I2C 7-bit Address AD5274 Digital Rheostat ADM1177 Hot Swap Controller ATSHA204 CryptoAuthentication M41T62 Real-Time Clock 24LC128 Serial EEPROM I2C2 I2C2 I2C2 I2C2 I2C1 0101110 1011011 1100100 1101000 1010001 2 Table 3. PIC I C Peripheral Address Map. Flash Pin CS SCLK SI SO WP HOLD PIC Port RB10 RB11 RB12 RB13 RB14 RB15 Table 4. PIC Flash Connections.
NetFPGA-1G-CML™ Board Reference Manual Figure 2. Pmod Connectors, End View. 14 FMC Expansion Connector The NetFPGA-1G includes a VITA-57 compatible FMC (FPGA Mezzanine Card) carrier connector. A High Pin Count (HPC) connector is used to provide the maximum possible compatibility with a variety of commercially available mezzanine cards.
NetFPGA-1G-CML™ Board Reference Manual Appendix A: Manufacturing Test The following hardware is required to run all NetFPGA-1G Manufacturing tests: • • • • • • • • • • • • • 1x HiTechGlobal PCI Express Test/SMA Breakout Board 8x SMA to SMA cable, 24” 2x Ethernet cables 1x NetFGPA-7 FMC Test Card 1x SD card, any size, loaded with an ASCII text file named “message.txt” 1x Micro (male) to Type A (female) USB adapter 1x USB thumb drive loaded with the production test bitstream, “mfg_test.
NetFPGA-1G-CML™ Board Reference Manual Appendix B: FPGA Pin Constraints The following list provides LOC and IOSTANDARD constraints for the main peripheral pins connected to the FPGA. This information can be used in a design UCF file with Xilinx ISE Design Suite, a design XDC file with Xilinx Vivado Design Suite, or with various interface generators included with Xilinx Coregen and MIG.
NetFPGA-1G-CML™ Board Reference Manual NET ddr3_addr[1] LOC = Y2 IOSTANDARD = SSTL15; NET ddr3_addr[2] LOC = W3 IOSTANDARD = SSTL15; NET ddr3_addr[3] LOC = W5 IOSTANDARD = SSTL15; NET ddr3_addr[4] LOC = AB2 IOSTANDARD = SSTL15; NET ddr3_addr[5] LOC = W1 IOSTANDARD = SSTL15; NET ddr3_addr[6] LOC = AC2 IOSTANDARD = SSTL15; NET ddr3_addr[7] LOC = U2 IOSTANDARD = SSTL15; NET ddr3_addr[8] LOC = AB1 IOSTANDARD = SSTL15; NET ddr3_addr[9] LOC = V1 IOSTANDARD = SSTL15; NET ddr3_addr[10]
NetFPGA-1G-CML™ Board Reference Manual QDRII+ Port Name IO Location IO Standard Type NET qdriip_d[0] LOC = V8 IOSTANDARD = HSTL_I; NET qdriip_d[1] LOC = V7 IOSTANDARD = HSTL_I; NET qdriip_d[2] LOC = W9 IOSTANDARD = HSTL_I; NET qdriip_d[3] LOC = Y11 IOSTANDARD = HSTL_I; NET qdriip_d[4] LOC = Y8 IOSTANDARD = HSTL_I; NET qdriip_d[5] LOC = Y7 IOSTANDARD = HSTL_I; NET qdriip_d[6] LOC = W10 IOSTANDARD = HSTL_I; NET qdriip_d[7] LOC = Y10 IOSTANDARD = HSTL_I; NET qdriip_d[8] LOC = V9 I
NetFPGA-1G-CML™ Board Reference Manual NET qdriip_q[14] LOC = AA20 IOSTANDARD = HSTL_I_DCI; NET qdriip_q[15] LOC = AD20 IOSTANDARD = HSTL_I_DCI; NET qdriip_q[16] LOC = AC17 IOSTANDARD = HSTL_I_DCI; NET qdriip_q[17] LOC = AB17 IOSTANDARD = HSTL_I_DCI; NET qdriip_sa[0] LOC = AC9 IOSTANDARD = HSTL_I; NET qdriip_sa[1] LOC = AF7 IOSTANDARD = HSTL_I; NET qdriip_sa[2] LOC = AA9 IOSTANDARD = HSTL_I; NET qdriip_sa[3] LOC = AD8 IOSTANDARD = HSTL_I; NET qdriip_sa[4] LOC = AC8 IOSTANDARD = HST
NetFPGA-1G-CML™ Board Reference Manual BPI Flash Port Name IO Location IO Standard Type NET bpi_clk_out LOC = C8 IOSTANDARD = LVCMOS33; NET bpi_we_n LOC = L18 IOSTANDARD = LVCMOS33; NET bpi_oe_n LOC = M17 IOSTANDARD = LVCMOS33; NET bpi_ce_n LOC = C23 IOSTANDARD = LVCMOS33; NET bpi_adv LOC = D20 IOSTANDARD = LVCMOS33; NET bpi_addr_cmd<0> LOC = J23 IOSTANDARD = LVCMOS33; NET bpi_addr_cmd<1> LOC = K23 IOSTANDARD = LVCMOS33; NET bpi_addr_cmd<2> LOC = K22 IOSTANDARD = LVCMOS33; NET bp
NetFPGA-1G-CML™ Board Reference Manual NET bpi_data<1> LOC = A25 IOSTANDARD = LVCMOS33; NET bpi_data<2> LOC = B22 IOSTANDARD = LVCMOS33; NET bpi_data<3> LOC = A22 IOSTANDARD = LVCMOS33; NET bpi_data<4> LOC = A23 IOSTANDARD = LVCMOS33; NET bpi_data<5> LOC = A24 IOSTANDARD = LVCMOS33; NET bpi_data<6> LOC = D26 IOSTANDARD = LVCMOS33; NET bpi_data<7> LOC = C26 IOSTANDARD = LVCMOS33; NET bpi_data<8> LOC = C24 IOSTANDARD = LVCMOS33; NET bpi_data<9> LOC = D21 IOSTANDARD = LVCMOS33; NET b
NetFPGA-1G-CML™ Board Reference Manual NET pcie-rx1_n LOC = K1; NET pcie-tx1_n LOC = L3; NET pcie-rx2_p LOC = M2; NET pcie-tx2_p LOC = N4; NET pcie-rx2_n LOC = M1; NET pcie-tx2_n LOC = N3; NET pcie-rx3_p LOC = M2; NET pcie-tx3_p LOC = N4; NET pcie-rx3_n LOC = M1; NET pcie-tx3_n LOC = N3; NET pcie-clk_p LOC = H6; NET pcie-clk_n LOC = H5; NET pcie-perstn LOC = L17 IOSTANDARD = LVCMOS33 NET pcie-wake LOC = K18 IOSTANDARD = LVCMOS33; NET pcie-prsnt LOC = AA7 IOSTANDARD = LVCMOS18
NetFPGA-1G-CML™ Board Reference Manual NET rgmii_rx_ctl_1 LOC = C13 IOSTANDARD = LVCMOS18; NET rgmii_rxc_1 LOC = E11 IOSTANDARD = LVCMOS18; NET rgmii_tx_ctl_1 LOC = F10 IOSTANDARD = LVCMOS18; NET rgmii_txc_1 LOC = E13 IOSTANDARD = LVCMOS18; NET rgmii_rxd_2[0] LOC = B15 IOSTANDARD = LVCMOS18; NET rgmii_rxd_2[1] LOC = F14 IOSTANDARD = LVCMOS18; NET rgmii_rxd_2[2] LOC = C14 IOSTANDARD = LVCMOS18; NET rgmii_rxd_2[3] LOC = H12 IOSTANDARD = LVCMOS18; NET rgmii_txd_2[0] LOC = J13 IOSTANDA
NetFPGA-1G-CML™ Board Reference Manual PIC Interface Port Name IO Location IO Standard Type NET pic2fpga_sck LOC = AA17 IOSTANDARD = LVCMOS18; NET pic2fpga_sdo LOC = V16 IOSTANDARD = LVCMOS18; NET pic2fpga_ss_n LOC = W16 IOSTANDARD = LVCMOS18; NET pic2fpga_gpi00 LOC = W18 IOSTANDARD = LVCMOS18; NET pic2fpga_gpi01 LOC = V17 IOSTANDARD = LVCMOS18; NET pic2fpga_sdi LOC = W15 IOSTANDARD = LVCMOS18; NET fpga2pic_sck LOC = W14 IOSTANDARD = LVCMOS18; NET fpga2pic_sdi LOC = V14 IOSTANDARD
NetFPGA-1G-CML™ Board Reference Manual NET pmod_ja_10 LOC = E21 IOSTANDARD = LVCMOS33; NET pmod_jb_1 LOC = F20 IOSTANDARD = LVCMOS33; NET pmod_jb_2 LOC = E15 IOSTANDARD = LVCMOS33; NET pmod_jb_3 LOC = H18 IOSTANDARD = LVCMOS33; NET pmod_jb_4 LOC = G19 IOSTANDARD = LVCMOS33; NET pmod_jb_7 LOC = H17 IOSTANDARD = LVCMOS33; NET pmod_jb_8 LOC = J21 IOSTANDARD = LVCMOS33; NET pmod_jb_9 LOC = L19 IOSTANDARD = LVCMOS33; NET pmod_jb_10 LOC = F18 IOSTANDARD = LVCMOS33; FMC Connector IOSTAND
NetFPGA-1G-CML™ Board Reference Manual NET FMC_LA07_N LOC = AC26; NET FMC_LA08_P LOC = AD26; NET FMC_LA08_N LOC = AE26; NET FMC_LA09_P LOC = Y25; NET FMC_LA09_N LOC = Y26; NET FMC_LA10_P LOC = W21; NET FMC_LA10_N LOC = V21; NET FMC_LA11_P LOC = W25; NET FMC_LA11_N LOC = W26; NET FMC_LA12_P LOC = W23; NET FMC_LA12_N LOC = W24; NET FMC_LA13_P LOC = U22; NET FMC_LA13_N LOC = V22; NET FMC_LA14_P LOC = R26; NET FMC_LA14_N LOC = P26; NET FMC_LA15_P LOC = T24; NET FMC_LA15_N LOC =
NetFPGA-1G-CML™ Board Reference Manual NET FMC_LA23_N LOC = N24; NET FMC_LA24_P LOC = U17; NET FMC_LA24_N LOC = T17; NET FMC_LA25_P LOC = T18; NET FMC_LA25_N LOC = T19; NET FMC_LA26_P LOC = M21; NET FMC_LA26_N LOC = M22; NET FMC_LA27_P LOC = N26; NET FMC_LA27_N LOC = M26; NET FMC_LA28_P LOC = R16; NET FMC_LA28_N LOC = R17; NET FMC_LA29_P LOC = K25; NET FMC_LA29_N LOC = K26; NET FMC_LA30_P LOC = N19; NET FMC_LA30_N LOC = M20; NET FMC_LA31_P LOC = P19; NET FMC_LA31_N LOC = P2
NetFPGA-1G-CML™ Board Reference Manual NET FMC_HA04_N LOC = U25; NET FMC_HA05_P LOC = V26; NET FMC_HA05_N LOC = U26; NET FMC_HA06_P LOC = AD25; NET FMC_HA06_N LOC = AE25; NET FMC_HA07_P LOC = AD21; NET FMC_HA07_N LOC = AE21; NET FMC_HA08_P LOC = AE22; NET FMC_HA08_N LOC = AF22; NET FMC_HA09_P LOC = R18; NET FMC_HA09_N LOC = P18; NET FMC_HA10_P LOC = U16; NET FMC_HA10_N LOC = N16; NET FMC_HA11_P LOC = Y20; NET FMC_HA11_N LOC = U21; NET FMC_CLK0_M2C_N LOC = P21; NET FMC_CLK0_M2
NetFPGA-1G-CML™ Board Reference Manual NET FMC_DP1_C2M_P LOC = D2 NET FMC_DP2_M2C_N LOC = B5; NET FMC_DP2_M2C_P LOC = B6; NET FMC_DP2_C2M_N LOC = A3; NET FMC_DP2_C2M_P LOC = A4; NET FMC_DP3_M2C_N LOC = G3; NET FMC_DP3_M2C_P LOC = G4; NET FMC_DP3_C2M_N LOC = F1; NET FMC_DP3_C2M_P LOC = F2; NET FMC_GBTCLK0_M2C_N LOC = F5; NET FMC_GBTCLK0_M2C_P LOC = F6; NET FMC_GBTCLK1_M2C_N LOC = D5; NET FMC_GBTCLK1_M2C_P LOC = D6; Copyright Digilent, Inc. All rights reserved.
